Using X9 Versus X18 Qdr Sram Parts - Intel IXP28XX Manual

IXP28XX Network Processor
QDR SRAM
4.4.1
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The IXP2800 SRAM memory interface is logically 32 bits wide. The read and write data buses are
physically two bytes wide each and are double-clocked. Each byte has a parity bit written and
checked on data writes and reads, respectively. The byte enables select bytes to write for data that
is less than 32 bits. The SRAM controller supports QDRII two-word bursts at speeds of up to 233
MHz.

Using x9 Versus x18 QDR SRAM Parts

When using x18 parts with four-SRAM load topology, there are serious signal integrity issues in
the DATA-READ cycle when one of the SRAMs is sending data and the IXP28XX network
processor is receiving (reading) the data from the SRAM that is driving. For example, the three
stubs of the other non-sending SRAMs could cause severe signal reflections that would deteriorate
the noise margin as well as the timing in the signal.
Using "star" topology, four electrical loads can be achieved on one side of the PCB; however, it is
recommended that simulation first verify that timing meets the specification and that signal
integrity is maintained.
With a two-SRAM load topology, the DATA-READ cycle's signal integrity issue is less serious
than in the four-SRAM load because there is only one stub hanging on the net. The more stubs the
net has, the more serious and severe the reflections become due to serious mismatching in the line
impedance.
During the DATA-WRITE cycle or in the ADDRESS net, the IXP28XX network processor sends
data to all of the SRAMs and thus, there are no hanging stubs that would cause severe reflections.
This means that performance is acceptable with four SRAM loads in the WRITE and ADDRESS
operations, but not in the DATA-READ operation.
For these reasons, it was necessary to split the DATA bus — that is, DATA-READ and
DATA-WRITE — into halves, each with a 2-SRAM load that is nine bits wide for designs that
implement a four-SRAM load topology. Using x9 SRAM devices provides clean signalling during
READ operations; see Figure 23.
Hardware Design Guide