Intel IXP28XX Manual page 6

IXP28XX Network Processor
Contents
21 Clocking Scheme for a QDR Interface Driving Four SRAMs...................................................... 54
22 QDR SRAM Connections ........................................................................................................... 57
23 Topologies for Using x9 Versus x18 QDR SRAM Parts ............................................................. 59
24 IXP2800 Width-Expanded QDR Interface .................................................................................. 60
25 Ingress IXP28XX Network Processor QDR Modular Channel Depth-Expanded QDR Interface 61
26 Ingress IXP2800 Network Processor QDR Modular Channel, Four-Load QDR Interface.......... 61
27 QDR Address Signals - Balanced T-Topology ......................................................................... 66
28 QDR Address Routing - T-Topology with Daisy-Chain Branches ............................................ 66
29 QDR Address Signal Trace Width/Spacing Routing................................................................... 67
30 D (Data Out) Routing Topology .................................................................................................. 68
31 QDR D Signal Trace Width/Spacing Routing ............................................................................. 69
32 Q (Data In) Routing Topology..................................................................................................... 70
33 QDR Q Signal Trace Width/Spacing Routing ............................................................................. 71
34 QDR K and K# Routing Topology............................................................................................... 72
35 QDR K and K# Signal Trace Width/Spacing Routing ................................................................. 73
36 QDR C, C#, CIN, and CIN# Routing Topology ........................................................................... 74
37 QDR C, C#, CIN, CIN# Signal Trace Width/Spacing Routing .................................................... 75
38 QDR Control RPE# and WPE# Signals Routing Topology ........................................................ 76
39 QDR Control RPE# and WPE# Signal Trace Width/Spacing Routing........................................ 77
40 QDR Control BWE# Signals Routing Topology .......................................................................... 78
41 Control BWE# Signal Trace Width/Spacing Routing .................................................................. 79
42 QDR SRAM VREF Generation ................................................................................................... 80
43 Resistive QDR VREF Divider Example ...................................................................................... 80
44 Voltage QDR VREF Divider Example for Each QDR Channel ................................................... 81
45 Address, D, CONTROL, Q, and K-Clocks Topologies ............................................................... 82
46 C, C#, CIN, and CIN# Clocks Topologies................................................................................... 83
47 QDR SRAM Routing Recommendations .................................................................................... 84
48 Four-QDR SRAM Load Routing Recommendations .................................................................. 85
49 Example Interconnects on the IXP28XX Network Processor, with a Two-QDRII SRAM Load
per Channel ................................................................................................................................ 86
50 Trace Length from IXP28XX Network Processor to SRAM (C, K, SA, D, and R/W_BW) .......... 87
51 Trace Length from SRAM to IXP28XX Network Processor (Q Data) ......................................... 87
52 QDR 0 Routing on Layer 13 - Adjacent QDR Clamshell Pairs ................................................... 89
53 QDR 1 Routing on Layer 12 - Adjacent QDR Clamshell Pairs ................................................... 90
54 TCAM and QDR SRAM Placement ............................................................................................ 91
55 Routing Recommendations for QDR SRAM and TCAM Routing ............................................... 92
56 QDR Signal from IXP28XX Network Processor to Tee Point on Layer 12 ................................. 93
57 QDR Signal Tee Point Arms Routed on Signal Layers 4 and 13 ............................................... 94
58 SPI-4 Clock Configuration for Dual Network Processors ......................................................... 102
59 CSIX Flow Control Interfaces: Simplex and Full Duplex Modes............................................... 103
60 LVDS Routing as Signal Pairs .................................................................................................. 105
61 Topology 1 - Two Unique PCBs Connected ............................................................................. 106
62 Topology 2 - Two Unique PCBs with Signal Loopback Through Connectors .......................... 107
63 PCI Subsystem ......................................................................................................................... 112
64 PPCI Address/Data Signal Topology........................................................................................ 113
65 PPCI Clock Signals Topology................................................................................................... 114
66 Address/Data Signals with IDSEL Topology (Showing Only the Ingress
Intel® IXP28XX Network Processor) ........................................................................................ 115
67 SPCI Address/Data Signal Topology........................................................................................ 116
68 SPCI Clock Signals Topology................................................................................................... 117
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