Rdram; Ixmb2800 Rdram Subsystem Design - Intel IXP28XX Manual

RDRAM

Note: RDRAM Powerdown and Nap modes are not supported.
3.1
Hardware Design Guide
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The Intel IXP2800 and Intel
DRAM (RDRAM) channels. Each of the controllers independently accesses its own RDRAMs,
and can operate concurrently with the other controllers (i.e., they are not operating as a single,
wider memory). DRAM provides high-density, high-bandwidth storage and is often used for data
buffers.
RDRAM sizes of 64, 128, 256, and 512 Mbytes, and 1 Gbyte are supported. However, each of the
channels must have the same number, size, and speed of RDRAMs populated. Each channel can be
populated with one to four per bank for short-channel, and one RIMM for long-channel.
Up to two Gbytes of DRAM are supported. If less than two Gbytes of memory is available, the
upper part of the address space is not used. It is also possible (for system cost and area savings) to
have channels 0 and 1 populated with channel 2 empty, or channel 0 populated with channels 1 and
2 empty.
Reads and writes to RDRAM are generated by Microengines, Intel XScale
(external Bus Masters and DMA Channels). The controllers also do refresh and calibration cycles
to the RDRAMs, transparently to software.
Hardware interleaving of addresses (also called striping) provides balanced access to all populated
channels; the interleave size is 128 bytes. Interleaving helps to maintain utilization of available
bandwidth by spreading consecutive accesses to multiple channels. The interleaving is done in the
hardware so that the three channels appear to software as a single, contiguous memory space.
ECC (Error Correcting Code) is supported, but can be disabled. Enabling ECC or parity requires
that x18 RDRAMs be used; if ECC is disabled, x16 RDRAMs can be used. ECC can detect and
correct all single-bit errors, and detect all double-bit errors. When ECC is enabled, partial writes
(of less than eight bytes) must be done as read-modify-writes.
It is not required to implement all three RDRAM channels, however if only a single channel is
implemented it MUST be channel 0. If two channels are implemented then it MUST be channels 0
and 1. No other channels are supported in these modes. Note that unused RSL I/Os do not require
termination. Also note that designs that do not implement all channels are still required to provide
power to all of the RSL I/O power pins as this is a common supply with the device.

IXMB2800 RDRAM Subsystem Design

The IXMB2800 network processor base card RDRAM subsystem design is implemented using
NexMod* memory module solution from High Connection Density, Inc. This solution provides a
scalable, high-speed memory in space-constrained applications for networking, communications,
and other markets. Using this solution minimizes the amount of space required to get the maximum
amount of memory, in this case 256 MB per channel, and facilitates the RDRAM interface design.
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IXP2850 Network Processors have controllers for three Rambus*
IXP28XX Network Processor
RDRAM
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core, and PCI
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