Intel IXP28XX Manual page 4

IXP28XX Network Processor
Contents
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
5 MSF (SPI-4/CSIX/FC) ................................................................................................................. 101
5.1
5.2
5.3
5.4
6 PCI............................................................................................................................................... 111
6.1
6.2
4
Downloaded from Elcodis.com electronic components distributor
QDR SRAM Interface ......................................................................................................... 57
4.4.1 Using x9 Versus x18 QDR SRAM Parts ................................................................ 58
4.4.1.1 Examples of the QDR Interface ............................................................. 60
4.4.2 Signal Groups ........................................................................................................ 62
4.4.3 QDR Signal Mapping ............................................................................................. 62
4.4.4 ClamShell Configuration of SRAMs....................................................................... 63
4.4.5 QDR SRAM Input/Output Timing Specifications.................................................... 64
4.4.5.1 IXP2800 Input Timing ............................................................................ 64
4.4.5.2 IXP2800 Output Timing.......................................................................... 64
4.4.6 QDR Signal Group Package Trace Length............................................................ 64
QDR SRAM Routing Rules................................................................................................. 65
4.5.1 QDR Trace Requirements ..................................................................................... 65
4.5.2 QDR SRAM Address Topology ............................................................................. 65
4.5.3 QDR SRAM D (Data Out) Topology ...................................................................... 68
4.5.4 QDR SRAM Q (Data In) Topology......................................................................... 70
4.5.5 QDR SRAM K, K# Clock Topologies ..................................................................... 71
4.5.5.1 Relationship between Address, Control, Data-OUT and K-Clock.......... 73
4.5.6 QDR SRAM C, C#, CIN, CIN# Clock Topologies .................................................. 74
4.5.7 QDR SRAM RPE#, WPE#, BWE# Control Topologies ......................................... 76
QDR SRAM VREF Generation ........................................................................................... 79
TCAM/SRAM/Coprocessor Interface.................................................................................. 81
4.7.1 TCAM/SRAM/Coprocessor Interface - Base Card Side ...................................... 81
4.7.1.1 Interface Topologies .............................................................................. 81
IXDP2800 QDR Implementation Guidelines....................................................................... 84
4.8.1 Routing for a Four-QDR SRAM Topology ............................................................. 84
4.8.2 Determining Loopclock Length for QDRII SRAM Used by IXDP2800 Advanced
Development Platform ........................................................................................... 85
4.8.3 QDR SRAM Alternating Routing Layers ................................................................ 89
IXDP2800 TCAM Implementation....................................................................................... 90
4.9.1 TCAM and QDR SRAM Placement ....................................................................... 90
4.9.2 QDR SRAM and TCAM Routing Implementation .................................................. 92
QDR SRAM and TCAM Routing......................................................................................... 93
QDR SRAM Design Review Checklist................................................................................ 94
Package Trace Lengths for QDR Signals........................................................................... 95
Media and Switch Fabric Interface ................................................................................... 101
5.1.1 SPI-4.2................................................................................................................. 101
5.1.2 CSIX .................................................................................................................... 102
5.1.3 Flow Control Bus ................................................................................................. 103
Routing Recommendations for LVDS Signals .................................................................. 104
5.2.1 LVDS Trace Requirements.................................................................................. 104
5.2.2 LVDS Trace Characteristics for IXDP2800 Advanced Development Platform .... 104
5.2.3 Design Review Checklist ..................................................................................... 104
5.2.4 LVDS Routing Example ....................................................................................... 105
Simulation Results for LVDS Signals on IXDP2800 Advanced Development Platform.... 106
Package Trace Lengths for LVDS_Diff Signals ................................................................ 108
PCI Controller ................................................................................................................... 111
PCI Interface..................................................................................................................... 111