Qdr Clocking Scheme; Sram Controller Configurations; Clocking Scheme For A Qdr Interface Driving Four Srams - Intel IXP28XX Manual

IXP28XX Network Processor
QDR SRAM
4.2
Figure 21.
4.2.1
Note: All of the SRAMs on a given channel must be the same size.
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significant changes in results or may lead to non-working design altogether. That is why it is
strongly recommended that developers thoroughly simulate any new designs or modifications
before committing to any new modifications.

QDR Clocking Scheme

The controller drives out a pair of K clocks (K and K#), and a pair of C clocks (C and C#). The C
and C# clocks externally return to the controller for reading data.
diagram of the clocking scheme for a QDR interface driving four SRAM chips.

Clocking Scheme for a QDR Interface Driving Four SRAMs

Termination
C0IN/C0IN#
Intel®
K0/K0#
IXP2800
C0/C0#
Network
C1/C1#
Processor
K1/K1#
C1IN/C1IN#
Termination

SRAM Controller Configurations

Each channel has enough address pins (24) to support up to 64 Mbytes of SRAM. The SRAM
controllers can directly generate multiple port enables (up to four pairs) to allow for depth
expansion; two pairs of pins are dedicated for port-enables. Smaller RAMs use fewer address
signals than the number provided to accommodate the largest RAMs, so some address pins – 23:20
– are configurable as either address or port-enable, based on the control status register (CSR)
setting, as shown in Table 14.
Figure 21 shows the clock
Clam-shelled SRAMS
Package Balls
K/K#
C/C#
C0/C0#
C1/C1#
C/C#
K/K#
Package Balls
Hardware Design Guide
A9234-03