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IXP28XX Network Processor
MSF (SPI-4/CSIX/FC)
5.2
5.2.1
5.2.2
5.2.3
104
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Routing Recommendations for LVDS Signals
LVDS Trace Requirements
The following is a list of LVDS trace requirements:
•
Differential signals must be routed as pairs with a 100-Ω differential impedance.
•
Each leg of a differential pair should be matched by length, within a tolerance of 10 mils.
•
A differential pair should be matched by length, within a tolerance of 100 mils.
•
Connectors can be used, but must be simulated.
•
Differential pair signals should be routed entirely on a single layer on inner layers of the PCB
LVDS Trace Characteristics for IXDP2800 Advanced
Development Platform
The LVDS trace characteristics are implemented as follows on the IXDP2800 Advanced
Development Platform:
•
The differential pair was routed with a minimum 4-mil trace width and a 10-mil trace pitch
(6-mil spacing between lines); these characteristics provide a 50-Ω trace and a 92-Ω
differential impedance.
•
Routing the differential pair with a 4-mil trace width and a 15-mil trace pitch between signal
pairs (11-mil spacing between lines) yields a better impedance match at the expense of routing
density.
Design Review Checklist
The following is a list of items that should be reviewed when implementing the LVDS interface
schematic design:
•
ZQ pins must be tied together through a 100-Ω resistor.
•
PREEMP pins must be terminated to V
•
Unused Receive Parity pins RPAR_H/L must be tied to logic 1 – i.e., RPAR_H = 1,
RPAR_L = 0.
•
Receive Protocol RPROT_H/L must be set accordingly for protocol that is being imple-
mented. For SPI-4 the differential pair must be set to a logic 0 and for CSIX to a logic 1 state:
— SPI-4 = 0, i.e., RPROT_H = 0, RPROT_L = 1
— CSIX = 1, i.e., RPROT_H = 1, RPROT_L = 0
.
SS
Hardware Design Guide
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