Qdr Sram C, C#, Cin, Cin# Clock Topologies; Qdr C, C#, Cin, And Cin# Routing Topology; Qdr C, C#, Cin, And Cin# Signal Group Routing Guidelines - Intel IXP28XX Manual

IXP28XX Network Processor
QDR SRAM
4.5.6
Figure 36.
Table 27.
74
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It is important to mention that the above two formulas are not independent but rather interrelated
and must be satisfied simultaneously. If adjustments are made to the lengths or topologies of these
signals then it is strongly recommended that simulations are performed to ensure that the signals
are properly aligned.

QDR SRAM C, C#, CIN, CIN# Clock Topologies

This output clock pair provides a user-controlled means of tuning SRAM device output data. The
rising edge of C is used as the output timing reference for first output data. The rising edge of C# is
used as the output reference for second output data. Ideally, C# is 180 degrees out of phase with C.
Figure 36 illustrates the routing topology for QDR C, C#, CIN, and CIN#.

QDR C, C#, CIN, and CIN# Routing Topology

C-Clk signal
C, C# and CIN, CIN#
®
Intel
IXP2800 Driver
Cout - Clock
C, C#
Intel ®
IXP2800 Receiver
Cin - Clock
CIN, CIN#
On-Die Termination
Table 27 provides routing guidelines for the QDR C, C#, CIN, and CIN# signal groups.
QDR C, C#, CIN, and CIN# Signal Group Routing Guidelines (Sheet 1 of 2)
Parameter
Signal Group
Topology
Reference Plane
Characteristic Trace Impedance
RTT
Nominal Trace Width
Nominal Trace Separation
Group spacing
A
B
Routing Guideline
C, C#, CIN, CIN#
Point-to-Point
Ground
50 Ω ±10%
50 Ω ±1% on-die termination at IXP28XX receiver
5 mils
20 - 25 mils
Isolation from all other signals is 20 mils
Top SRAM
Bottom SRAM
B3957-01
Hardware Design Guide