Intel IXP28XX Manual page 138

IXP28XX Network Processor
Slowport
7.1.2.2.3
Note: The actual protocol of these control signals varies depending on the interface configuration mode
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different operating modes that are implemented to support a variety of microprocessor interfaces,
with different address and data widths. For more information on the operating modes, refer to the
Intel® IXP2800 Network Processor Hardware Reference Manual.
Write Transactions
During write transactions to 16- and 32-bit devices, the 8-bit data from the IXP28XX SP_AD bus
must be packed into 16 bits (WORD) or 32 bits (DWORD). Extra signals, SP_CP, SP_OE_L, and
SP_DIR, provide the management of packing and unpacking operations and control which device
drives the bus during read and write transactions.
(1, 2, 3, or 4). The remainder of this section concentrates on the Mode 3 protocol, the mode that
would be used to interface to the Intel
Figure 84 shows an example of discrete components and their associated signal connections that
could be used to implement the glue logic.
signals presented to the glue logic during a write transaction with the Slowport configured for
Mode 3, i.e., SP_PCR = 0x3, and the address and data size set to 32-bit, i.e., SP_ADC = 0x33.
®
IXF1010 10-port 100/1000Mbps Ethernet MAC.
Figure 85 shows the timing of the Slowport interface
Hardware Design Guide