Burst, Pipelined Read Request With Wait States, 32-Bit Bus - Intel 80960HA Datasheet

Figure 44. Burst, Pipelined Read Request with Wait States, 32-Bit Bus
PMCON
Function
Bit
Value
CLKIN
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
W/R
A3:2
D31:0,
DP3:0
WAIT
BLAST
DT/R
DEN
PCHK
Datasheet
External
Pipe-
Ready
Burst
Lining
Control
29 28 24
ON
X Enabled
1
1
x
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1
A 2 1
ADS
00
1. Non-pipelined request concludes, pipelined reads begin.
2. Pipelined reads conclude, non-pipelined requests begin.
Parity
Bus
Odd
N
Parity Enable
Width XDA
23-22 21 20 19-16
32-Bit
X Enabled
xxxx
x 1
10
D 1 D 1 D
Valid
01 10
IN IN
D
D
80960HA/HD/HT
N N N
RDD
WDD WAD
15-14 12-8 7-6
X X 1
X
xxxxx
xx 01
A'
1 2 1
D
Valid
11 Valid
IN
IN
D
D
N
RAD
4-0
2
00010
D'
2
In-
valid
In-
valid
In-
valid
IN
D'
69