A Summary Of Aligned And Unaligned Transfers For 32-Bit Regions - Intel 80960HA Datasheet

80960HA/HD/HT
Figure 54. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions
Short-Word
Load/Store
Word
Load/Store
Double-Word
Load/Store
NOTES:
1. All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes
adjacent requests to occur for full words to the same address.
78
0 4
Byte Offset
Word Offset
0 1
Short Request (Aligned)
Short Requests (Unaligned)
Short Request (Aligned)
Word Request (Aligned)
8 12
2 3
Byte, Byte Requests
Trey, Byte, Requests
Short, Short Requests
Byte, Trey, Requests
One Double-Word Burst (Aligned)
Trey, Byte, Trey, Byte, Requests
Short, Short, Short, Short Requests
Byte, Trey, Byte, Trey, Requests
Word, Word Requests
16 20 24
4 5 6
One Double-Word
Request (Aligned)
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