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About This Document
This document describes the parametric performance of Intel's 80960Hx embedded superscalar
microprocessors. Detailed descriptions for functional topics, other than parametric performance,
are published in the i960
In this document, '80960Hx' and 'i960 Hx processor' refer to the products described in
Throughout this document, information that is specific to each is clearly indicated.
Figure 1. 80960Hx Block Diagram
Interrupt
Port
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Intel 80960Hx Processor
The Intel 80960Hx processor provides new performance levels while maintaining backward
compatibility (pin
family of i960 32-bit, RISC-style, embedded processors allows customers to create scalable
designs that meet multiple price and performance points. This is accomplished by providing
processors that may run at the bus speed or faster using Intel's clock multiplying technology
(see
Table
sophisticated instruction scheduler that allows the processor to sustain a throughput of two
instructions every core clock, with a peak performance of three instructions per clock. The
80960Hx-series comprises three processors, which differ in the ratio of core clock speed to external
bus speed.
Table 1. 80960Hx Product Description
Product
80960HA
80960HD
80960HT
† Processor inputs are 5 V tolerant.
1. The 80960Hx is not "drop-in" compatible in an 80960Cx-based system. Customers may design systems that accept either 80960Hx or Cx
processors.
Datasheet
®
Hx Microprocessor User's Guide (272484).
JTAG Port
16 Kbyte, Four-Way Set-Associative
Timers
Programmable
Interrupt Controller
Multiply/Divide Unit
Register-Side
Execution Unit
Machine Bus
64-bit SRC1 Bus
64-bit SRC2 Bus
64-bit DST Bus
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and software) with the i960 CA/CF processor. This newest member of the
1). The 80960Hx core is capable of issuing 150 million instructions per second, using a
Core
1x
2x
3x
Instruction Prefetch Queue
Instruction Cache
128-Bit Cache Bus
Parallel Instruction Scheduler
Memory-Side
Machine Bus
Six-Port Register File
32-bit Base Bus
128-bit Load Bus
128-bit Store Bus
Voltage
Operating Frequency (bus/core)
†
3.3 V
25/25, 33/33, 40/40
†
3.3 V
25/50, 33/66, 40/80
†
3.3 V
80960HA/HD/HT
Table
Guarded Memory Unit
Memory Region Configuration
Bus Controller
Bus Request Queues
Data Cache
8 Kbyte, Four-Way Set-Associative
Data RAM - 2 Kbyte
Register Cache - 5 to 15 sets
Address Generation Unit
25/75
1.
Control
Address
Data
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