Non-Burst, Non-Pipelined Requests Without Wait States - Intel 80960HA Datasheet

32-bit high-performance superscalar processor
Table of Contents

Advertisement

Figure 32. Non-Burst, Non-Pipelined Requests without Wait States
PMCON
Datasheet
External
Pipe-
Function
Ready
Burst
Lining
Control
Bit
29
28
24
Disabled
OFF
Disabled
Value
0
0
0
NOTE:
Bits 31-30, 27-25, 13, and 5 are reserved.
A
CLKIN
ADS
A31:2, SUP,
D/C,
BE3:0,
LOCK, CT3:0
W/R
BLAST
DT/R
DEN
WAIT
D31:0,
DP3:0
PCHK
Bus
Parity
Odd
N
Parity
Enable
Width
XDA
23-22
21
20
19-16
X
X
Enabled
0
x
xx
1
0000
D
A
D
Valid
Valid
Out
In
80960HA/HD/HT
N
N
N
N
RAD
RDD
WDD
WAD
15-14
12-8
7-6
4-0
0
0
0
0
00
00000
00000
00
A
D
Valid
In
57

Advertisement

Table of Contents
loading

This manual is also suitable for:

80960hd80960ht

Table of Contents