Intel 80960HA Datasheet page 4

Contents
7 VCC5 Current-Limiting Resistor ................................................................................................. 38
8 AC Test Load.............................................................................................................................. 45
9 CLKIN Waveform........................................................................................................................ 46
10 Output Delay Waveform ............................................................................................................. 46
11 Output Delay Waveform ............................................................................................................. 46
12 Output Float Waveform .............................................................................................................. 47
13 Input Setup and Hold Waveform ................................................................................................ 47
14 NMI, XINT7:0 Input Setup and Hold Waveform.......................................................................... 47
15 Hold Acknowledge Timings ........................................................................................................ 48
16 Bus Backoff (BOFF) Timings ...................................................................................................... 48
17 TCK Waveform ........................................................................................................................... 49
18 Input Setup and Hold Waveforms for T
19 Output Delay and Output Float for TBSOV1 and TBSOF1 ........................................................ 50
20 Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 ....................................... 50
21 Input Setup and Hold Waveform for TBSIS2 and TBSIH2 ......................................................... 50
22 Rise and Fall Time Derating at 85 °C and Minimum VCC.......................................................... 51
23 I Active (Power Supply) vs. Frequency................................................................................... 51
CC
24 I Active (Thermal) vs. Frequency............................................................................................ 52
CC
25 Output Delay or Hold vs. Load Capacitance .............................................................................. 52
26 Output Delay vs. Temperature ................................................................................................... 53
27 Output Hold Times vs. Temperature .......................................................................................... 53
28 Output Delay vs. VCC ................................................................................................................ 53
29 Cold Reset Waveform ................................................................................................................ 54
30 Warm Reset Waveform .............................................................................................................. 55
31 Entering ONCE Mode................................................................................................................. 56
32 Non-Burst, Non-Pipelined Requests without Wait States ........................................................... 57
33 Non-Burst, Non-Pipelined Read Request with Wait States ........................................................ 58
34 Non-Burst, Non-Pipelined Write Request with Wait States ........................................................ 59
35 Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus ........................................ 60
36 Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus ............................................. 61
37 Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus ........................................ 62
38 Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus ............................................. 63
39 Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus ............................................. 64
40 Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus ............................................... 65
41 Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus ........................................ 66
42 Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus ............................................. 67
43 Burst, Pipelined Read Request without Wait States, 32-Bit Bus ................................................ 68
44 Burst, Pipelined Read Request with Wait States, 32-Bit Bus ..................................................... 69
45 Burst, Pipelined Read Request with Wait States, 8-Bit Bus ....................................................... 70
46 Burst, Pipelined Read Request with Wait States, 16-Bit Bus ..................................................... 71
47 Using External READY............................................................................................................... 72
48 Terminating a Burst with BTERM ............................................................................................... 73
49 BREQ and BSTALL Operation ................................................................................................... 74
50 BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle. ........................ 75
51 HOLD Functional Timing ............................................................................................................ 76
52 LOCK Delays HOLDA Timing..................................................................................................... 77
53 FAIL Functional Timing............................................................................................................... 77
54 A Summary of Aligned and Unaligned Transfers for 32-Bit Regions.......................................... 78
55 A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued) ...................... 79
56 A Summary of Aligned and Unaligned Transfers for 16-Bit Bus................................................. 80
4
and TBSIH1.......................................................... 49
BSIS1
Datasheet