Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus - Intel 80960HA Datasheet

Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus
PMCON
Function
Value
A31:4, SUP,
CT3:0, D/C,
Datasheet
External
Pipe-
Ready
Burst
Lining
Width
Control
Bit
29 28 24 23-22
32-Bit
ON
X Disabled
1
x 0
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1
A
CLKIN
ADS
LOCK
W/R
A3:2
BE3:0
D31:0,
DP3:0
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
Bus Parity
Odd
N
Parity Enable
XDA
21 20 19-16
X
Enabled X
xxxx
x
1
10
A'
1 1
D
Valid Valid
Valid Valid
IN
D
80960HA/HD/HT
N
N N N
RAD
RDD
WDD WAD
15-14 12-8 7-6 4-0
X X X
1
xx xxxxx xx
00001
2
D '
Invalid
Invalid
Invalid
IN
D'
67