A Summary Of Aligned And Unaligned Transfers For 32-Bit Regions (Continued) - Intel 80960HA Datasheet

Figure 55. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued)
Byte Offset
Word Offset
Triple-Word
Load/Store
Quad-Word
Load/Store
NOTES:
1. All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes
adjacent requests to occur for full words to the same address.
Datasheet
0 4 8
0 1 2
12 16 20
3 4 5
One Three-Word
Request (Aligned)
Trey, Byte, Trey, Byte,
Trey, Byte Requests
Short, Short, Short, Short
Short, Short, Short Requests
Byte, Trey, Byte, Trey, Byte, Trey Requests
Word, Word,
Word Requests
Word, Word,
Word Requests
One Four-Word
Request (Aligned)
Trey, Byte, Trey, Byte, Trey, Byte
Trey, Byte Requests
8 Short Requests
Byte, Trey, Byte, Trey,
Byte, Trey, Byte, Trey, Requests
80960HA/HD/HT
24
6
Word,
Word,
Word
Requests
4 Word
Requests
4 Word
Requests
79