Burst, Pipelined Read Request With Wait States, 8-Bit Bus - Intel 80960HA Datasheet

80960HA/HD/HT
Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus
PMCON
Function
Bit
Value
CLKIN
A31:4, SUP,
CT3:0, D/C,
LOCK
BE1/A1,
BE0/A0
D31:0,
DP3:0
WAIT
BLAST
PCHK
70
External
Pipe-
Ready
Burst
Lining
Control
28 24
29
ON
X Enabled
1
1
x
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A 2 1
1
ADS
W/R
A3:2
A1:0 = 00
DT/R
DEN
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
Parity
Bus
Odd
N
Parity Enable
Width XDA
23-22 21 20 19-16
8-Bit
X Enabled
X
xxxx
00 x 1
D 1 D 1 D
Valid
A3:2 = 00, 01, 10, or 11
A1:0 = 01 A1:0 = 10 A1:0 = 11
D7:0 D7:0 D7:0
Byte 1
Byte 0 Byte 2
N
N
N N
RDD
WDD WAD
15-14 12-8 7-6
X X 1
xxxxx
xx 01
00010
2
A'
1 2 1 D'
D
In-
Valid
valid
In-
valid
In-
Valid
valid
In-
Valid
valid
D7:0
D7:0
Byte 3
D'
RAD
4-0
2
Datasheet