Motorola MC68306 User Manual page 14

LIST OF TABLES
Table Page
Number Title Number
Table 2-1. Bus Signal Summary ............................................................................... 2-3
Table 2-2. Chip Select Signal Summary ................................................................... 2-3
Table 2-3. DRAM Controller Signal Summary .......................................................... 2-3
Table 2-4. Interrupt and Parallel Port Signal Summary ............................................ 2-4
Table 2-5. Clock and Mode Control Signal Summary............................................... 2-4
Table 2-6. Serial Module Signal Summary ............................................................... 2-4
Table 2-7. JTAG Signal Summary ............................................................................ 2-5
Table 2-8. Function Code Outputs ............................................................................ 2-7
Table 2-9. Data Strobe Control of Data Bus ............................................................. 2-8
Table 3-1. DTACK, BERR, and HALT Assertion Results ......................................... 3-24
Table 3-2. BERR and HALT Negation Results ......................................................... 3-25
Table 4-1. Processor Data Formats.......................................................................... 4-3
Table 4-2. Effective Addressing Modes .................................................................... 4-4
Table 4-3. Notation Conventions .............................................................................. 4-5
Table 4-4. EC000 Core Instruction Set Summary .................................................... 4-8
Table 4-5. Exception Vector Assignments ................................................................ 4-16
Table 4-6. Exception Grouping and Priority .............................................................. 4-22
Table 5-1. MC68306 Memory Map ........................................................................... 5-2
Table 5-2. Chip Select Match Bits ............................................................................ 5-11
Table 5-3. DRAM Address Multiplexer...................................................................... 5-13
Table 5-4. DRAM Bank Match Bits ........................................................................... 5-15
Table 6-1. PMx and PT Control Bits ......................................................................... 6-20
Table 6-2. B/Cx Control Bits ..................................................................................... 6-20
Table 6-3. CMx Control Bits...................................................................................... 6-21
Table 6-4. SBx Control Bits ...................................................................................... 6-22
Table 6-5. RCSx Control Bits.................................................................................... 6-25
Table 6-6. TCSx Control Bits .................................................................................... 6-26
Table 6-7. MISCx Control Bits .................................................................................. 6-27
Table 6-8. TCx Control Bits ...................................................................................... 6-28
Table 6-9. RCx Control Bits ...................................................................................... 6-28
Table 6-10. Counter/Timer Mode and Source Select Bits ........................................ 6-30
MOTOROLA MC68306 USER'S MANUAL xv