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ADDR
AS
R/W
UDS/LDS
DATA
DTACK
Figure 3-31. Pseudo-Asynchronous Write Cycle
3.8 SYNCHRONOUS OPERATION
In some systems, external devices use the system clock to generate DTACK and other
asynchronous input signals. This synchronous operation provides a closely coupled
design with maximum performance, appropriate for frequently accessed parts of the
system. For example, memory can operate in the synchronous mode, but peripheral
devices operate asynchronously. For a synchronous device, the designer uses explicit
timing information shown in AC Electrical Specifications—Read and Write Cycles.
These specifications define the state of all bus signals relative to a specific state of the
processor clock.
The standard M68000 bus cycle consists of four clock periods (eight bus cycle states)
and, optionally, an integral number of clock cycles inserted as wait states. Wait states are
inserted as required to allow sufficient response time for the external device. The following
state-by-state description of the bus cycle differs from those descriptions in 3.1.1 Read
Cycle and 3.1.2 Write Cycle by including information about the important timing
parameters that apply in the bus cycle states.
STATE 0
The bus cycle starts in S0, during which the clock is high. At the rising edge
of S0, the function code for the access is driven externally. Parameter #6A
defines the delay from this rising edge until the function codes are valid.
Also, the R/W signal is driven high; parameter #18 defines the delay from
the same rising edge to the transition of R/W . The minimum value for
parameter #18 applies to a read cycle preceded by a write cycle; this value
is the maximum hold time for a low on R/W beyond the initiation of the read
cycle.
MOTOROLA
11
20A
22
55
26
MC68306 USER'S MANUAL
28
29
C
3- 33
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