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local loopback mode or multidrop mode, the receiver operates even though this
command is selected. If the receiver is already disabled, this command has no effect.
Do Not Use—Do not use this bit combination because the result is indeterminate.
6.4.1.6 RECEIVER BUFFER (DURB). The receiver buffer contains three receiver holding
registers and a serial shift register. The channel's RxDx pin is connected to the serial shift
register. The holding registers act as a FIFO. The CPU reads from the top of the stack
while the receiver shifts and updates from the bottom of the stack when the shift register
has been filled (see Figure 6-4).
RB7–RB0—These bits contain the character in the receiver buffer.
6.4.1.7 TRANSMITTER BUFFER (DUTB). The transmitter buffer consists of two registers,
the transmitter holding register and the transmitter shift register (see Figure 6-4). The
holding register accepts characters from the bus master if the TxRDY bit in the channel's
DUSR is set. A write to the transmitter buffer clears the TxRDY bit, inhibiting any more
characters until the shift register is ready to accept more data. When the shift register is
empty, it checks to see if the holding register has a valid character to be sent (TxRDY bit
cleared). If there is a valid character, the shift register loads the character and reasserts
the TxRDY bit in the channel's DUSR. Writes to the transmitter buffer when the channel's
DUSR TxRDY bit is clear and when the transmitter is disabled have no effect on the
transmitter buffer.
TB7–TB0—These bits contain the character in the transmitter buffer.
6.4.1.8 INPUT PORT CHANGE REGISTER (DUIPCR). The DUIPCR shows the current
state and the change-of-state for the IP0, IP1, and IP2 pins.
MOTOROLA
DURBA, DURBB
7
6
5
RB7
RB6
RB5
RB4
RESET:
0
0
0
Read Only
DUTBA, DUTBB
7
6
5
TB7
TB6
TB5
TB4
RESET:
0
0
0
Write Only
DUIPCR
7
6
5
0
COS2
COS1
COS0
RESET:
0
0
0
Read Only
MC68306 USER'S MANUAL
4
3
2
1
RB3
RB2
RB1
0
0
0
0
4
3
2
1
TB3
TB2
TB1
0
0
0
0
4
3
2
1
1
IP2
IP1
0
1
IP2
IP1
0
RB0
0
0
TB0
0
0
IP0
IP0
6-29
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