Table of Contents
Advertisement
8.7 AC ELECTRICAL SPECIFICATIONS—READ AND WRITE
CYCLES
(Continued)
Num
6
20A
AS Asserted to R/W Low (Write)
2
21
Address Valid to R/W Low (Write)
2
21A
FC Valid to R/W Low (Write)
2
22
R/ W Low to LDS, UDS Asserted (Write)
23
CLKOUT Low to Data-Out Valid (Write)
2
25
AS, LDS, UDS Negated to Data-Out Invalid (Write)
2
26
Data-Out Valid to LDS, UDS Asserted (Write)
5
27
Data-In Valid to CLKOUT Low (Setup Time on Read)
2
28
AS, LDS, UDS Negated to DTACK Negated (Asynchronous
Hold)
29
AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read)
29A
AS, LDS, UDS Negated to Data-In High Impedance
30
AS, LDS, UDS Negated to BERR Negated
31 2,5
DTACK Asserted to Data-In Valid (Setup Time)
32
HALT and RESET Input Transition Time
47 5
Asynchronous Input Setup Time
48 3
BERR Asserted to DTACK Asserted
53
Data-Out Hold from CLKOUT High
55
R/ W Asserted to Data Bus Impedance Change
56 4
HALT/RESET Pulse Width
NOTES:
1.
For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the
maximum columns.
2.
Actual value depends on clock period.
3.
If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR
is an asynchronous input using the asynchronous input setup time (#47).
4.
For power-up, the MC68306 must be held in the reset state for 100 ms to allow stabilization of on-chip
circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the
controller.
5.
If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data
setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time
(#27) for the following clock cycle.
6.
When AS and R/W are equally loaded ( 20%), subtract 5 ns from the values given in these columns.
7.
The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before
asserting BGACK.
8.
The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be
reasserted.
9.
AS is always asserted, regardless of whether it is mapped to internal or external resources. If the designer
wishes to decode more chip selects than are provided, use one of CS0–7 as the enable for the external decode.
8-6
Characteristic
MC68306 USER'S MANUAL
16.67 MHz
Min
Max
Unit
—
10
ns
0
—
ns
30
—
ns
30
—
ns
—
30
ns
15
—
ns
15
—
ns
5
—
ns
0
110
ns
0
—
ns
—
90
ns
0
—
ns
—
50
ns
—
150
ns
5
—
ns
10
—
ns
0
—
ns
0
—
ns
10
—
Clks
MOTOROLA
Advertisement
Table of Contents
