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Bits 7, 6, 3, 2—Reserved
COS2, COS1, COS0—Change-of-State
1 = A change-of-state (high-to-low or low-to-high transition), lasting longer than 25–
50 s has occurred at the corresponding IPx input. When these bits are set, the
DUACR can be programmed to generate an interrupt to the CPU.
0 = No change-of-state has occurred since the last time the CPU read the DUIPCR.
A read of the DUIPCR also clears the DUISR COS bit.
IP2, IP1, IP0—Current State
Starting two serial clock periods after reset, the IPx bits reflect the state of the IPx pins.
If a CTS≈ pin is detected as asserted at that time, the associated COSx bit will be set,
which will initiate an interrupt if the corresponding IECx bit of the DUACR register is
enabled.
1 = The current state of the respective IPx input is logic one (negated, if used as
CTS ).
0 = The current state of the respective IPx input is logic zero (asserted, if used as
CTS ).
6.4.1.9 AUXILIARY CONTROL REGISTER (DUACR). The DUACR selects which baud
rate is used and controls the handshake of the transmitter/receiver.
BRG—Baud Rate Generator Set Select
1 = Set 2 of the available baud rates is selected.
0 = Set 1 of the available baud rates is selected. Refer to 6.4.1.4 Clock-Select
Register (DUCSR) for more information on the baud rates.
CTMS2–0— Counter/Timer Mode and Source Select
Table 6-10 lists the counter/timer mode and source select bit fields.
6-30
DUACR
7
6
5
BRG
CTMS2 CTMS1 CTMS0
RESET:
0
0
0
Write Only
MC68306 USER'S MANUAL
4
3
2
1
–
IEC2
IEC1
0
0
0
0
0
IEC0
0
MOTOROLA
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