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1111 = A31–A17 must match CSA31–CSA17 in chip select address match
Table 5-2 shows the entire range of address bits that must match for a chip select to
occur.
A31
A30
A29
0000
x
x
0001
•
x
0010
•
•
0011
•
•
0100
•
•
0101
•
•
0110
•
•
0111
•
•
1000
•
•
1001
•
•
1010
•
•
1011
•
•
1100
•
•
1101
•
•
1110
•
•
1111
•
•
x = Address bit is a don't care, CSA bit must be 0 to allow match.
• = Address bit must match CSA bit for chip select to occur.
CSDT3–0—Chip Select DTACK Wait State Selection
This field determines whether automatic DTACK is returned, and how many wait states
are inserted if automatic DTACK is enabled. When automatic DTACK is selected, the
write portion of a TAS indivisible cycle is the same length as a normal write cycle to the
same location. Any external DTACK generation circuit must recognize that AS remains
asserted throughout a read-write indivisible cycle, if it supports TAS.
0000 = Automatic DTACK, 0 wait states
0001 = Automatic DTACK, 1 wait state
0010 = Automatic DTACK, 2 wait states
0011 = Automatic DTACK, 3 wait states
0100 = Automatic DTACK, 4 wait states
0101 = Automatic DTACK, 5 wait states
0110 = Automatic DTACK, 6 wait states
0111 = Automatic DTACK, 7 wait states
MOTOROLA
Table 5-2. Chip Select Match Bits
A28
A27
A26
x
x
x
x
x
x
x
x
x
x
x
x
•
x
x
x
•
•
x
x
•
•
•
x
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MC68306 USER'S MANUAL
A25
A24
A23
A22
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
•
x
x
x
•
•
x
x
•
•
•
x
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1000 = Automatic DTACK, 8 wait states
1001 = Automatic DTACK, 9 wait states
1010 = Automatic DTACK, 10 wait states
1011 = Automatic DTACK, 11 wait states
1100 = Automatic DTACK, 12 wait states
1101 = Automatic DTACK, 13 wait states
1110 = Automatic DTACK, 14 wait states
1111 = No automatic DTACK, external
DTACK required
A21
A20
A19
A18
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
•
x
x
x
•
•
x
x
•
•
•
x
•
•
•
•
•
•
•
•
A17
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
•
5- 11
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