Figure 7-1. Test Access Port Block Diagram - Motorola MC68306 User Manual

An overview of the MC68306 implementation of IEEE 1149.1 is shown in Figure 7-1. The
MC68306 implementation includes a 16-state controller, a 3-bit instruction register, and
four test registers (a 1-bit bypass register, a 124-bit boundary scan register, a 3-bit module
mode register, and a 32-bit ID register). This implementation includes a dedicated TAP
consisting of the following signals:
TRST — active low JTAG logic reset (with pullup).
TCK — test clock input to synchronize the test logic (with pulldown).
TMS — test mode select input (with an internal pullup resistor) that is sampled on the
rising edge of TCK to sequence the TAP controller's state machine.
TDI — test data input (with an internal pullup resistor) that is sampled on the rising
edge of TCK.
TDO — three-state test data output that is actively driven in the shift-IR and shift-DR
controller states. TDO changes on the falling edge of TCK.
TDI
TRST
TMS
TAP
CTLR
TCK
7-2
TEST DATA REGISTERS
123
BOUNDARY SCAN REGISTER
(124 BITS)
BYPASS
DECODER
2
3-BIT INSTRUCTION REGISTER

Figure 7-1. Test Access Port Block Diagram

MC68306 USER'S MANUAL
2 0
MODE
31 0
ID
M
0 U
X
0
ID = 2040101D
M
U
TDO
X
MOTOROLA