Figure 8-3. Read Cycle Timing Diagram - Motorola MC68306 User Manual

CLKOUT
FC2–FC0
A23–A1
AS
LDS / UDS
R/W
OE
DTACK
DATA IN
BERR / BR
(NOTE 2)
HALT / RESET
ASYNCHRONOUS
INPUTS
(NOTE 1)
NOTES:
1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK, BERR, IRQx) guarantees
their recognition at the next falling edge of the clock.
2. BR need fall at this time only to ensure being recognized at the end of the bus cycle.
MOTOROLA
S0 S1 S2 S3
6A
8
6
15
11
13
11A
9
9A
48
47
32
56

Figure 8-3. Read Cycle Timing Diagram

MC68306 USER'S MANUAL
S4 S5 S6 S7
14
47
27
31
47
47
32
47
12
12A
28
29
29A
30
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