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6.4.1.3 STATUS REGISTER (DUSR). The DUSR indicates the status of the characters in
the FIFO and the status of the channel transmitter and receiver.
RB—Received Break
1 = An all-zero character of the programmed length has been received without a stop
bit. The RB bit is only valid when the RxRDY bit is set. Only a single FIFO
position is occupied when a break is received. Further entries to the FIFO are
inhibited until the channel RxDx returns to the high state for at least one-half bit
time, which is equal to two successive edges of the internal or external 1 clock
or 16 successive edges of the external 16 clock.
The received break circuit detects breaks that originate in the middle of a
received character. However, if a break begins in the middle of a character, it
must persist until the end of the next detected character time.
0 = No break has been received.
6-22
Table 6-4. SBx Control Bits
SB3
SB2
SB1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
DUSRA, DUSRB
7
6
5
RB
FE
PE
RESET:
0
0
0
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MC68306 USER'S MANUAL
SB0
Length 6-8 Bits
0
0.563
1
0.625
0
0.688
1
0.750
0
0.813
1
0.875
0
0.938
1
1.000
0
1.563
1
1.625
0
1.688
1
1.750
0
1.813
1
1.875
0
1.938
1
2.000
4
3
2
1
OE
TxEMP
TxRDY
FFULL
0
0
0
0
Length 5 Bits
1.063
1.125
1.188
1.250
1.313
1.375
1.438
1.500
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
0
RxRDY
0
MOTOROLA
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