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Access Error, 4-1
Exception, 4-21
Addressing Modes, 4-4
Index Sizing and Scaling, 4-4
Indexing, 4-4
Postincrement, Predecrement, Offset, and
Program Counter Indirect, 4-4
Register Indirect, 4-4
AS, 3-4, 3-7, 3-16
Asynchronous Bus Arbitration Signals, 3-17
Asynchronous Mode, 3-32
Autovector, 5-5
Automatic DTACK Generation, 5-16
Baud Rate Generator, 6-3, 6-4, 6-7
BERR, 3-4, 3-7, 3-10, 3-37
BG, 3-16
Boundary Scan Bit Definitions, 7-5
Boundary Scan, 7-1
Bit Definitions, 7-5
Bus Arbitration, 3-12
Bus Error Exception, 3-28, 4-20
Bus Grant Signal, 3-16
Bus Timeout Period Register, 5-4
Byte Read Cycle Flowchart, 3-2
Chip Select Configuration Register, 5-9
Counter Mode, 6-16
Counter/Timer, 6-16
CTLR, 6-34
CTUR, 6-34
Data Formats, 4-3
Data Types
Access Errors, 4-1
M-bit, 4-14
Denormalized Numbers, 4-3
Infinities, 4-3
NANs, 4-3
Normalized Numbers, 4-3
Zeros, 4-3
Double Bus Fault, 3-29
DRAM
Configuration Register, 5-14
Refresh Register, 5-13
DTACK, 3-4, 3-7, 3-10, 3-33, 3-37
DUACR, 6-30
MOTOROLA
— A —
— B —
— C —
— D —
MC68306 USER'S MANUAL
I N D E X
DUCR, 6-26
DUCSR, 6-24
DUCUR, 6-33
DUIMR, 6-33
DUIP, 6-34
DUIPCR, 6-29
DUISR, 6-31
DUIVR, 6-34
DUMR1, 6-18
DUMR2, 6-20
DUOP, 6-35
DUOPCR, 6-35
DURBA, 6-29
DURBB, 6-29
DUSR, 6-22
DUTBA, 6-29
DUTBB, 6-29
Exception Handler, 4-14
Exceptions, 4-12
Exception Vector, 4-14
Table, 4-12
FC2–FC0, 3-4, 3-7
FIFO Stack, 6-11
HALT, 3-28
I/O Driver Routines, 6-37
Initialization Routines, 6-36
Instructions
STOP, 4-1
TRAP, TRAPV, CHK, RTE, and DIV, 4-12
Interrupt, 4-1
Acknowledge Bus Cycle, 4-12
Control Register, 5-5
Handling Routine, 6-37
Priorities, 4-17
Priority Mask, 4-12
Request Signals, 6-3
Request, 4-17
Status Register, 5-6
Priority Mask, 4-12
— E —
— F —
— H —
— I —
Index-1
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