Figure 3-20. Three-Wire Bus Arbitration Timing Diagram-Special Case - Motorola MC68306 User Manual

BUS THREE-STATED
BG ASSERTED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED
CLK
S0
BR
BG
BGACK
FC2–FC0
A31–A1
AS
UDS
LDS
R/W
DTACK
D15–D0
PROCESSOR
Figure 3-20. Three-Wire Bus Arbitration Timing Diagram—Special Case
MOTOROLA
BUS RELEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE
BGACK NEGATED INTERNAL
BGACK SAMPLED
BGACK NEGATED
S2 S4 S6
ALTERNATE BUS MASTER
MC68306 USER'S MANUAL
S0 S2 S4 S6
PROCESSOR
S0
3- 21