Figure 3-28 Fully Asynchronous Read Cycle; Figure 3-29. Fully Asynchronous Write Cycle - Motorola MC68306 User Manual

ADDR
AS
R/W
UDS/LDS
DATA
DTACK
ADDR
AS
R/W
UDS/LDS
DATA
DTACK
In the asynchronous mode, the accessed device operates independently of the frequency
and phase of the system clock. For example, the MC68681 dual universal asynchronous
receiver/transmitter (DUART) does not require any clock-related information from the bus
master during a bus transfer. Asynchronous devices are designed to operate correctly
with processors at any clock frequency when relevant timing requirements are observed.
A device can use a clock at the same frequency as the system clock (e.g., 8, 10, or 12.5
MHz), but without a defined phase relationship to the system clock. This mode of
operation is pseudo-asynchronous; it increases performance by observing timing
parameters related to the system clock frequency without being completely synchronous
with that clock. A memory array designed to operate with a particular frequency processor
but not driven by the processor clock is a common example of a pseudo-asynchronous
device.
The designer of a fully asynchronous system can make no assumptions about address
setup time, which could be used to improve performance. With the system clock frequency
known, the slave device can be designed to decode the address bus before recognizing
an address strobe. Parameter #11 (refer to AC Electrical Specifications—Read and
Write Cycles) specifies the minimum time before address strobe during which the
address is valid.
MOTOROLA

Figure 3-28 Fully Asynchronous Read Cycle

Figure 3-29. Fully Asynchronous Write Cycle

MC68306 USER'S MANUAL 3- 31