Figure 8-4. Write Cycle Timing Diagram - Motorola MC68306 User Manual

CLKOUT
FC2–FC0
A23–A1
AS
(NOTE 2)
LDS / UDS
R/W
(NOTE 2)
UW, LW
DTACK
DATA OUT
BERR / BR
(NOTE 3)
HALT / RESET
ASYNCHRONOUS
INPUTS
(NOTE 1)
NOTES:
1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK, BERR, IRQx) guarantees
their recognition at the next falling edge of the clock.
2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge
of S2 (specification #20A).
3. BR need fall at this time only to ensure being recognized at the end of the bus cycle.
8-8
S0 S1 S2 S3
8
6
21
15
9
11
11A
20A
17
20
18
22
13
15A
55
26
23
7
48
47
32
56

Figure 8-4. Write Cycle Timing Diagram

MC68306 USER'S MANUAL
S4 S5 S6 S7
14
9
14A
9A
47
47
47
32
47
12
12A
28
53
25
30
MOTOROLA