Intel Xeon Processor E5-1600 Datasheet page 177

Table 7-16. DDR3 and DDR3L Signal DC Specifications (Sheet 2 of 2)
Symbol Parameter
V Output Low Voltage
OL
V Output High Voltage
OH
Reference Clock Signal
R DDR3 Clock Buffer On
ON
Resistance
Command Signals
R DDR3 Command Buffer On
ON
Resistance
R DDR3 Reset Buffer On
ON
Resistance
V Output Low Voltage, Signals
OL_CMOS1.5v
DDR_RESET_ C{01/23}_N
V Output High Voltage, Signals
OH_CMOS1.5v
DDR_RESET_ C{01/23}_N
I Input Leakage Current
IL_CMOS1.5v
Control Signals
R DDR3 Control Buffer On
ON
Resistance
DDR01_RCOMP[0 COMP Resistance
]
DDR01_RCOMP[1 COMP Resistance
]
DDR01_RCOMP[2 COMP Resistance
]
DDR23_RCOMP[0 COMP Resistance
]
DDR23_RCOMP[1 COMP Resistance
]
DDR23_RCOMP[2 COMP Resistance
]
DDR3 Miscellaneous Signals
V Input Low Voltage
IL
DRAM_PWR_OK_C{01/23}
V Input High Voltage
IH
DRAM_PWR_OK_C{01/23}
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The voltage rail V which will be set to 1.50 V or 1.35 V nominal depending on the voltage of all DIMMs connected to the
CCD
processor.
3. V is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
IL
4. V is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
IH
5. V and V may experience excursions above V
IH OH
specifications. Refer to Section
6. This is the pull down driver resistance. Refer to processor signal integrity models for I/V characteristics. Reset drive does not
have a termination.
7. R is the termination on the DIMM and not controlled by the processor. Please refer to the applicable DIMM datasheet.
VTT_TERM
8. The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.
9. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for
implementation details. DDR01_RCOMP[2:0] and DDR23_RCOMP[2:0] resistors are terminated to VSS.
10. Input leakage current is specified for all DDR3 signals.
11. DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 +300 mV and -200 mV and the
edge must be monotonic.
12. The DDR01/23_RCOMP error tolerance is ± 15% from the compensated value.
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
Min
(V
21
16
25
0.9*V
CCD
-100
21
128.7
25.839
198
128.7
25.839
198
0.55*VCC
D + 0.3
. However, input signal drivers must comply with the signal quality
CCD
7.9.
Typ
/ 2)* (R /(R +R
CCD ON ON VTT_TERM
V - ((V / 2)* (R /
CCD CCD ON
(R +R ))
ON VTT_TERM
130
26.1
200
130
26.1
200
Max Units Notes
)) V 2, 7
V 2, 5, 7
31 6
24 6
75 6
0.2*V V 1,2
CCD
V 1,2
+100 A 1,2
31 6
131.3 9,12
26.361 9,12
202 9,12
131.3 9,12
26.361 9,12
202 9,12
0.55*VCC V 2, 3,
D - 0.2 11, 13
V 2, 4, 5,
11, 13
177
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