Direct Media Interface Gen 2 (Dmi2); Intel® Quickpath Interconnect (Intel® Qpi); Pci Express* Lane Partitioning And Direct Media Interface Gen 2 (Dmi2) - Intel Xeon Processor E5-1600 Datasheet

Figure 1-3.

PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)

Port 0
DMI / PCIe
Transaction
Link
Physical
0...3
X4
DMI
1.2.3

Direct Media Interface Gen 2 (DMI2)

• Serves as the chip-to-chip interface to the Intel® C600 Chipset
• The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2
• Operates at PCI Express* 1.0 or 2.0 speeds
• Transparent to software
• Processor and peer-to-peer writes and reads with 64-bit address support
• APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined "End of
Interrupt" broadcast message when initiated by the processor.
• System Management Interrupt (SMI), SCI, and SERR error indication
• Static lane numbering reversal support
• Supports DMI2 virtual channels VC0, VC1, VCm, and VCp
1.2.4 Intel® QuickPath Interconnect (Intel® QPI)
• Compliant with Intel QuickPath Interconnect v1.1 standard packet formats
• Implements two full width Intel QPI ports
• Full width port includes 20 data lanes and 1 clock lane
• 64 byte cache-lines
• Isochronous access support for Quality of Service (QoS), native 1 and 2 socket
platforms - Intel® Xeon® processor E5-1600 and E5-2600 product families only
18
Port 1
(IOU2)
PCIe
Transaction
Link
Physical
0...3 4...7 0...3
X4 X4 X4
Po rt 1a Po rt 1b Po rt 2a Po rt 2b
X8 X8
Po rt 1a Po rt 2a
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Port 2
(IOU0)
PCIe
Transaction
Link
Physical
4...7 8...11 12..15 0...3
X4 X4 X4 X4
Po rt 2c Po rt 2d Po rt 3a
X8
Po rt 2c
X16
Po rt 2a
Overview
Port 3
(IOU1)
PCIe
Transaction
Link
Physical
4...7 8...11 12..15
X4 X4 X4
Po rt 3b Po rt 3c Po rt 3d
X8 X8
Po rt 3a Po rt 3c
X16
Po rt 3a
Datasheet Volume One