Jtag And Tap Signals Dc Specifications; Serial Vid Interface (Svid) Dc Specifications - Intel Xeon Processor E5-1600 Datasheet

Table 7-19. SMBus DC Specifications (Sheet 2 of 2)
Symbol
V Input High Voltage
IH
V Output Low Voltage
OL
V Output High Voltage
OH
R Buffer On Resistance
ON
I Leakage Current
L
Signals DDR_SCL_C{01/23}, DDR_SDA_C{01/
23}
I Leakage Current
L
Signals PEHPSCL, PEHPSDA
Table 7-20. JTAG and TAP Signals DC Specifications
Symbol
V Input Low Voltage
IL
V Input High Voltage
IH
V Output Low Voltage
OL
(R = 500 ohm)
TEST
V Output High Voltage
OH
(R = 500 ohm)
TEST
R Buffer On Resistance
ON
Signals BPM_N[7:0], TDO, EAR_N
I Input Leakage Current
IL
Signals PREQ_N, TCK, TDI, TMS, TRST_N
I Input Leakage Current
IL
Signals BPM_N[7:0], TDO, EAR_N
(R = 50 ohm)
TEST
I Output Current
O
Signal PRDY_N
(R = 500 ohm)
TEST
Input Edge Rate
Signals: BPM_N[7:0], EAR_N, PREQ_N, TCK,
TDI, TMS, TRST_N
Note:
1. These signals are measured between VIL and VIH.
2. The signal edge rate must be met or the signal must transition monotonically to the asserted state.
Table 7-21. Serial VID Interface (SVID) DC Specifications (Sheet 1 of 2)
Symbol
V CPU I/O Voltage
TT
V Input Low Voltage
IL
Signals SVIDDATA, SVIDALERT_N
V Input High Voltage
IH
Signals SVIDDATA, SVIDALERT_N
V Output High Voltage
OH
Signals SVIDCLK, SVIDDATA
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
Parameter
Parameter
Parameter
Min Max
0.7*VTT
0.2*V
V
TT(max)
14
-100 +100
+900
Min Max
0.3*V
TT
0.7*V
TT
0.12*V
TT
0.88*V
TT
14
-50 +50
+900
-1.50 +1.50
0.05
Min Typ
VTT - 3% 1.05 VTT + 3%
0.3*V
0.7*V
TT
V
Units Notes
V
V
TT
V
A
A
Units Notes
V
V
V
V
A
A
mA
V/ns 1, 2
Max Units Notes
V
V 1
TT
V 1
V 1
TT(max)
179