Page 1 Dual-Core Intel® Xeon® Processor 5200 Series Datasheet August 2008 318590-005...
Page 2 The Dual-Core Intel® Xeon® Processor 5200 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Page 3: Table Of Contents
Processor Materials.................... 44 Processor Markings.................... 44 Processor Land Coordinates ................45 Land Listing......................47 Dual-Core Intel® Xeon® Processor 5200 Series Pin Assignments ......47 4.1.1 Land Listing by Land Name ..............47 4.1.2 Land Listing by Land Number ..............57 Signal Definitions ....................
Page 4 Debug Tools Specifications ..................113 Debug Port System Requirements ..............113 Target System Implementation................113 9.2.1 System Implementation................. 113 Logic Analyzer Interface (LAI) ................113 9.3.1 Mechanical Considerations ..............114 9.3.2 Electrical Considerations ................ 114 Dual-Core Intel® Xeon® Processor 5200 Series Datasheet...
Page 5 2-12 Differential Rising and Falling Edge Rates ............. 38 Processor Package Assembly Sketch ..............39 Dual-Core Intel® Xeon® Processor 5200 Series Package Drawing (Sheet 1 of 3) ..40 Dual-Core Intel® Xeon® Processor 5200 Series Package Drawing (Sheet 2 of 3) ..41 Dual-Core Intel®...
Page 6 2-10 PECI DC Electrical Limits..................25 2-11 Processor Absolute Maximum Ratings ..............27 2-12 Voltage and Current Specifications ...............28 2-13 Dual-Core Intel® Xeon® Processor E5200 Series andDual-Core Intel® Xeon® Processor X5200 Series and Dual-Core Intel® Xeon® Processor L5200 Series VCC Static and Transient Tolerance ..............31 2-14 AGTL+ Signal Group DC Specifications..............34...
Page 7: Revision History
Added product information for Dual-Core Intel® Xeon® Processor April 2008 L5200 Series. Corrected L1 cache size August 2008 Exposed L5215 Rev to keep in sync with Quad-Core Intel® Xeon® Processor 5400 Series Datasheet August 2008 No content changes § Dual-Core Intel® Xeon® Processor 5200 Series Datasheet...
Page 8 Dual-Core Intel® Xeon® Processor 5200 Series Datasheet...
Page 9: Introduction
IA-32 software. Some key features include on-die, primary 32-kB instruction cache ® and 32-kB write-back data cache in each core and 6 MB Level 2 cache with Intel Advanced Smart Cache architecture. The processors’ Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced effective bus latency and improved performance.
Page 10: Terminology
Further details on Intel Virtualization Technology can be found at http://developer.intel.com/technology/platform-technology/virtualization/index.htm. The Dual-Core Intel® Xeon® Processor 5200 Series is intended for high performance server and workstation systems. The Dual-Core Intel® Xeon® Processor 5200 Series supports a Dual Independent Bus (DIB) architecture with one processor on each bus, up to two processor sockets in a system.
Page 11 • Dual-Core Intel® Xeon® Processor L5238 - Intel 64-bit microprocessor intended for dual processor server blades and embedded servers. The Dual-Core Intel® Xeon® Processor L5238 is a lower voltage and lower power version of the Dual-Core Intel® Xeon® Processor L5200 Series supporting higher case temperatures.
Page 12 771 lands, and includes an integrated heat spreader (IHS). • LGA771 socket – The Dual-Core Intel® Xeon® Processor 5200 Series interfaces to the baseboard through this surface mount, 771 Land socket. See the LGA771 Socket Design Guidelines for details regarding this socket.
Page 13: State Of Data
Design Guidelines (TMDG) LGA771 Socket Mechanical Design Guide 313871 Dual-Core Intel® Xeon® Processor 5200 Series Boundary Scan Description 318588 Language (BSDL) Model Notes: Contact your Intel representative for the latest revision of these documents Document is available publicly at http://developer.intel.com.
Page 14 §...
Page 15: Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications
V . The on-die termination resistors are always enabled on the Dual-Core Intel® Xeon® Processor 5200 Series to control reflections on the transmission line. Intel chipsets also provide on-die termination, thus eliminating the need to terminate the bus on the baseboard for most AGTL+ signals.
Page 16: Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the Dual-Core Intel® Xeon® Processor 5200 Seriesis capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Page 17: Front Side Bus Clock (Bclk[1:0]) And Processor Clocking
Listed frequencies are not necessarily committed production frequencies. For valid processor core frequencies, see Dual-Core Intel® Xeon® Processor 5200 Series Specification Update. The lowest bus ratio supported by the Dual-Core Intel® Xeon® Processor 5200 Series is 1/6. 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]) Upon power up, the FSB frequency is set to the maximum supported by the individual processor.
Page 18: Pll Power Supply
Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines defines VID[7:0], VID7 and VID0 are not used on the Dual-Core Intel® Xeon® Processor 5200 Series; VID7 is always hard wired low at the voltage regulator.
Page 19 Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications The Dual-Core Intel® Xeon® Processor 5200 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage.
Page 20: Voltage Identification Definition
When the “111111” VID pattern is observed, the voltage regulator output should be disabled. Shading denotes the expected VID range of the Dual-Core Intel® Xeon® Processor 5200 Series The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see ®...
Page 21: Reserved, Unused, And Test Signals
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-4. Loadline Selection Truth Table for LL_ID[1:0] LL_ID1 LL_ID0 Description Reserved ® ® Dual-Core Intel Xeon Processor 5100 series, Dual-Core Intel® Xeon® Processor 5200 Series, and Quad-Core Intel® Xeon® Processor 5400 Series Reserved ®...
Page 22: Front Side Bus Signal Groups
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications The TESTHI signals must use individual pull-up resistors as detailed below. A matched resistor must be used for each signal: • TESTHI8 - cannot be grouped with other TESTHI signals • TESTHI9 - cannot be grouped with other TESTHI signals •...
Page 23: Agtl+ Signal Description Table
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-6. FSB Signal Groups (Sheet 2 of 2) Signal Group Type Signals CMOS Asynchronous Input Asynchronous A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, STPCLK# CMOS Asynchronous Output Asynchronous BSEL[2:0], VID[6:1]...
Page 24: Cmos Asynchronous And Open Drain Asynchronous Signals
Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The Dual-Core Intel® Xeon® Processor 5200 Series contains Digital Thermal Sensor (DTS) sprinkled both inside and outside the cores in a die.
Page 25: Input Device Hysteresis
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-10. PECI DC Electrical Limits Symbol Definition and Conditions Units Notes Input Voltage Range -0.150 Hysteresis 0.1 * V hysteresis Negative-edge threshold 0.275 * V 0.500 * V voltage Positive-edge threshold 0.550 * V...
Page 26: Mixing Processors
FSB frequency, core frequency, power segments, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel. Combining processors from different power segments is also not supported.
Page 27: Processor Dc Specifications
Flexible Motherboard Guidelines (FMB) The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the Dual-Core Intel® Xeon® Processor 5200 Series will have over certain time periods. The values are only estimates and actual specifications for future processors may differ.
Page 28: Voltage And Current Specifications
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-12. Voltage and Current Specifications (Sheet 1 of 2) 1, 11 Symbol Parameter Unit Notes VID range 0.850 1.3500 for processor core Table 2-13 Figure 2-5, 2, 3, 4, 6, 9...
Page 29 Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-12. Voltage and Current Specifications (Sheet 2 of 2) Symbol Parameter Unit Notes 1, 11 Thermal Design Current 6,14 CC_TDC (TDC) Dual-Core Intel® Xeon® Processor X5200 Series Launch - FMB Thermal Design Current...
Page 30: Dual-Core Intel® Xeon® Processor E5200 Series Load Current Versus Time
1.1 V. 17. I is specified while PWRGOOD and RESET# are asserted. CC_RESET Figure 2-2. Dual-Core Intel® Xeon® Processor E5200 Series Load Current versus Time 0 . 0 1 0 .1 10 0 10 0 0 Tim e Duration (s)
Page 31: Dual-Core Intel® Xeon® Processor L5200 Series Load Current Versus Time
Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than CC_TDC Not 100% tested. Specified by design characterization. Table 2-13. Dual-Core Intel® Xeon® Processor E5200 Series andDual-Core Intel® Xeon® Processor X5200 Series and Dual-Core Intel® Xeon® Processor L5200 Series...
Page 32: And Transient Tolerance Load Lines
Please refer to the appropriate platform design guide for details on VR implementation. values greater than 75A are not applicable for the Dual-Core Intel® Xeon® Processor E5200 Series. values greater than 50A are not applicable for the Dual-Core Intel® Xeon® Processor L5200 Series.
Page 33: And Transient Tolerance Load Lines
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Figure 2-6. Dual-Core Intel® Xeon® Processor X5200 Series V Static and Transient Tolerance Load Lines Icc [A] VID - 0.000 VID - 0.020 Maximum VID - 0.040 VID - 0.060 VID - 0.080 VID - 0.100...
Page 34: Cmos Signal Input/Output Group And Tap Signal Group Dc Specifications
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Notes: The V and V loadlines represent static and transient limits. Please see Section 2.13.2 for VCC CC_MIN CC_MAX overshoot specifications. Refer to Table 2-12 for processor VID information. Refer to Table 2-13...
Page 35: Vcc Overshoot Specification
0 V and V 2.13.2 Overshoot Specification The Dual-Core Intel® Xeon® Processor 5200 Series can tolerate short transient overshoot events where V exceeds the VID voltage when transitioning from a high- to-low current load condition. This overshoot cannot exceed VID + V...
Page 36: Agtl+ Fsb Specifications
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications 2.14 AGTL+ FSB Specifications Routing topologies are dependent on the processors supported and the chipset used in the design. Please refer to the appropriate platform design guidelines for specific implementation details. In most cases, termination resistors are not required as these are integrated into the processor silicon.
Page 37: Electrical Test Circuit
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-19. FSB Differential BCLK Specifications (Sheet 2 of 2) Symbol Parameter Unit Figure Notes Overshoot 1.150 2-10 Undershoot -0.300 2-10 Ringback Margin 0.200 2-10 Threshold Region 2-10 CROSS CROSS 0.100 + 0.100 Input Leakage Current ±...
Page 38: Differential Clock Waveform
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Figure 2-10. Differential Clock Waveform Overshoot BCLK1 Rising Edge Ringback Crossing Crossing Ringback Voltage Voltage Margin Threshold Region Falling Edge Ringback, BCLK0 Undershoot Tp = T1: BCLK[1:0] period Figure 2-11. Differential Clock Crosspoint Specification 550 mV 550 + 0.5 (VHavg - 700)
Page 39: Mechanical Specifications
Mechanical Specifications Mechanical Specifications The Dual-Core Intel® Xeon® Processor 5200 Series is packaged in a Flip Chip Land Grid Array (FC-LGA) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771 lands. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink.
Page 40: Dual-Core Intel® Xeon® Processor 5200 Series Package Drawing (Sheet 1 Of 3)
Mechanical Specifications Figure 3-2. Dual-Core Intel® Xeon® Processor 5200 Series Package Drawing (Sheet 1 of 3) Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal/Mechanical Design Guidelines.
Page 41: Dual-Core Intel® Xeon® Processor 5200 Series Package Drawing (Sheet 2 Of 3)
Mechanical Specifications Figure 3-3. Dual-Core Intel® Xeon® Processor 5200 Series Package Drawing (Sheet 2 of 3)
Page 42: Dual-Core Intel® Xeon® Processor 5200 Series Package Drawing (Sheet 3 Of 3)
Mechanical Specifications Figure 3-4. Dual-Core Intel® Xeon® Processor 5200 Series Package Drawing (Sheet 3 of 3)
Page 43: Processor Component Keepout Zones
For more information on the transient bend limits, please refer to the MAS document titled Manufacturing ® with Intel components using 771-land LGA package that interfaces with the motherboard via a LGA771 socket. Refer to the Dual-Core Intel® Xeon® Processor 5200 Series Thermal/Mechanical Design Guidelines (TMDG) for information on heatsink clip load metrology.
Page 44: Package Handling Guidelines
LGA771 socket, which meets the criteria outlined in the LGA771 Socket Design Guidelines. Processor Mass Specifications The typical mass of the Dual-Core Intel® Xeon® Processor 5200 Series is 21.5 grams [0.76 oz.]. This includes all components which make up the entire processor product. Processor Materials The Dual-Core Intel®...
Page 45: Processor Land Coordinates
Mechanical Specifications Figure 3-5. Processor Top-side Markings (Example) Mark Text (Production Mark): Legend: GROUP1LINE1 3400DP/6M/1600 GROUP1LINE1 GROUP1LINE2 Intel ® Xeon ® GROUP1LINE2 GROUP1LINE3 Proc# SXXX COO GROUP1LINE4 GROUP1LINE3 i (M) © ‘06 GROUP1LINE5 GROUP1LINE4 GROUP1LINE5 ATPO ATPO ATPO Note: 2D matrix is required for engineering samples only (encoded with ATPO-S/N).
Page 46: Processor Land Coordinates, Bottom View
Mechanical Specifications Figure 3-7. Processor Land Coordinates, Bottom View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Address / Socket 771 Common Clock / Quadrants...
Page 47: Land Listing
Land Listing Land Listing Dual-Core Intel® Xeon® Processor 5200 Series Pin Assignments This section provides sorted land list in Table 4-1 Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 a listing of all processor lands ordered by land number.
Page 48 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 3 of 20) (Sheet 4 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type D01# Source Sync Input/Output D41# Source Sync Input/Output...
Page 49 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 5 of 20) (Sheet 6 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type DSTBP1# Source Sync Input/Output RESERVED DSTBP2# Source Sync...
Page 50 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 7 of 20) (Sheet 8 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type RESERVED Power/Other RESET# Common Clk Input AE11 Power/Other...
Page 51 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 9 of 20) (Sheet 10 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type AH15 Power/Other AL15 Power/Other AH18 Power/Other AL18...
Page 52 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 11 of 20) (Sheet 12 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
Page 53 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 13 of 20) (Sheet 14 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type Power/Other AB29 Power/Other Power/Other AB30 Power/Other Power/Other...
Page 54 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 15 of 20) (Sheet 16 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type AG13 Power/Other AK28 Power/Other AG16 Power/Other AK29...
Page 55 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 17 of 20) (Sheet 18 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
Page 56 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 19 of 20) (Sheet 20 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
Page 57: Land Listing By Land Number
Land Listing 4.1.2 Land Listing by Land Number Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 2 of 20) (Sheet 1 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type...
Page 58 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 3 of 20) (Sheet 4 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type AD26 Power/Other Power/Other...
Page 59 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 5 of 20) (Sheet 6 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type AG18 Power/Other AH27...
Page 60 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 7 of 20) (Sheet 8 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type Power/Other AL18 Power/Other...
Page 61 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 9 of 20) (Sheet 10 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type AM26 Power/Other D10#...
Page 62 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 11 of 20) (Sheet 12 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type BNR# Common Clk Input/Output...
Page 63: Land Listing By Land Number
Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 13 of 20) (Sheet 14 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type Power/Other RESERVED D23#...
Page 64 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 15 of 20) (Sheet 16 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type Power/Other Power/Other Power/Other...
Page 65 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 17 of 20) (Sheet 18 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type STPCLK# CMOS Async Input...
Page 66 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 19 of 20) (Sheet 20 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type AP1# Common Clk Input/Output...
Page 67: Signal Definitions
ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. This signal must be connected to the appropriate pins on all Dual-Core Intel® Xeon® Processor 5200 Series FSB agents. ADSTB[1:0]# Address strobes are used to latch A[37:3]# and REQ[4:0]# on their rising and falling edge.
Page 68 Signal Definitions Table 5-1. Signal Definitions (Sheet 2 of 8) Name Type Description Notes BCLK[1:0] The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V CROSS...
Page 69 If a debug port connector is implemented in the system, DBR# is a no- connect on the Dual-Core Intel® Xeon® Processor 5200 Series package. DBR# is not a processor signal.
Page 70 CPUID Instruction application note. FORCEPR# The FORCEPR# (force power reduction) input can be used by the platform to cause the Dual-Core Intel® Xeon® Processor 5200 Series to activate the Thermal Control Circuit (TCC). GTLREF_ADD GTLREF_ADD determines the signal reference level for AGTL+ address and common clock input lands.
Page 71 • Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, refer to the ® Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3.
Page 72 These signals are not connected to the processor die. Both the bits 0 and 1 are logic 0 and pulled to ground on the Dual-Core Intel® Xeon® Processor 5200 Series package. PROCHOT# PROCHOT# (Processor Hot) will go active when the processor’s temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature.
Page 73 TRST# TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. The Dual-Core Intel® Xeon® Processor 5200 Series implements an CCPLL on-die PLL filter solution. The V input is used as a PLL supply CCPLL voltage.
Page 74 Xeon® Processor 5200 Series package. Notes: For this processor land on the Dual-Core Intel® Xeon® Processor 5200 Series, the maximum number of symmetric agents is one. Maximum number of priority agents is zero. For this processor land on the Dual-Core Intel® Xeon® Processor 5200 Series, the maximum number of symmetric agents is two.
Page 75: Thermal Specifications
Thermal Specifications Package Thermal Specifications The Dual-Core Intel® Xeon® Processor 5200 Series requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Page 76 Dual-Core Intel® Xeon® Processor 5200 Series in Embedded Thermal/Mechanical Design Guidelines (TMDG). The Dual-Core Intel® Xeon® Processor X5200 Series supports a dual Thermal Profile, either of which can be implemented. Both ensure adherence to the Intel reliability requirements. Thermal Profile A (see Figure 6-2;...
Page 77: Dual-Core Intel® Xeon® Processor E5200 Series Thermal Profile
Table 6-2 for discrete points that constitute the thermal profile. Implementation of the Dual-Core Intel® Xeon® Processor E5200 Series Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss.
Page 78: Dual-Core Intel® Xeon® Processor E5200 Series Thermal Profile Table
Thermal Specifications Table 6-2. Dual-Core Intel® Xeon® Processor E5200 Series Thermal Profile Table Power (W) (°C) CASE_MAX 43.0 44.8 46.5 48.3 50.1 51.9 53.6 55.4 57.2 58.9 60.7 62.5 64.2 66.0 Table 6-3. Dual-Core Intel® Xeon® Processor X5200 Series Thermal Specifications...
Page 79: Dual-Core Intel® Xeon® Processor X5200 Series Thermal Profiles A And B
Y = 0.235*x +42.2 Y = 0.235*x +42.2 Power [W] Power [W] Notes: The Dual-Core Intel® Xeon® Processor X5200 Series Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-4 Table 6-5 for discrete points that constitute the thermal profile.
Page 80: Dual-Core Intel® Xeon® Processor X5200 Series Thermal B Profile Table
Thermal Specifications Table 6-4. Dual-Core Intel® Xeon® Processor X5200 Series Thermal A Profile Table (Sheet 2 of 2) Power (W) (°C) CASE_MAX 54.0 55.1 56.3 57.5 58.7 59.8 61.0 Table 6-5. Dual-Core Intel® Xeon® Processor X5200 Series Thermal B Profile Table Power (W) (°C)
Page 81: Dual-Core Intel® Xeon® Processor L5200 Series Thermal Profile
Table 6-7 for discrete points that constitute the thermal profile. Implementation of the Dual-Core Intel® Xeon® Processor L5200 Series Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss.
Page 82: Dual-Core Intel® Xeon® Processor L5238 Thermal Profile
Table 6-9 for discrete points that constitute the thermal profile. Implementation of the Dual-Core Intel® Xeon® Processor L5238 Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss.
Page 83: Dual-Core Intel® Xeon® Processor L5215 Thermal Profile
= 1.5 * P + 45 CASE Nominal Short Term Power (W) Notes: Dual-Core Intel® Xeon® Processor L5215 Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-11 for discrete points that constitute the thermal profile.
Page 84: Thermal Metrology
Thermal Specifications Implementation of the Dual-Core Intel® Xeon® Processor L5215 Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss.
Page 85: Processor Thermal Features
Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2. The Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2 must both be enabled in BIOS for the processor to be operating within specifications. When both are enabled, Intel® Thermal Monitor 2 will be activated first and Intel®...
Page 86 Core Intel® Xeon® Processor 5200 Series Thermal/Mechanical Design Guidelines (TMDG) for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Intel® Thermal Monitor 1, is factory configured and cannot be modified. The Intel® Thermal Monitor 1 does not require any additional hardware, software drivers, or interrupt handling routines.
Page 87: On-Demand Mode
This mechanism is referred to as “On- Demand” mode and is distinct from the Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2 features. On-Demand mode is intended as a means to reduce system level power consumption.
Page 88: Prochot# Signal
6.2.5 THERMTRIP# Signal Regardless of whether or not Intel® Thermal Monitor 1 or Intel® Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the...
Page 89: Platform Environment Control Interface (Peci)
It uses a single wire, thus alleviating routing congestion issues. Figure 6-8 shows an example of the PECI topology in a system with Dual-Core Intel® Xeon® Processor 5200 Series. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices.
Page 90: Peci Specifications
Thermal Specifications Figure 6-9. Conceptual Fan Control Diagram of PECI-based Platforms TCC Activation TCC Activation CONTROL CONTROL Setting Setting Temperature Temperature PECI = 0 PECI = 0 Fan Speed Fan Speed (RPM ) (RPM ) PECI = -10 PECI = -10 M in M in PECI = -20...
Page 91: Gettemp0() Error Codes
Thermal Specifications 6.3.2.3 PECI Fault Handling Requirements PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. The PECI client is as reliable as the device that it is embedded in, and thus given operating conditions that fall under the specification, the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures.
Page 92 Thermal Specifications...
Page 93: Features
Address lands not identified in this table as configuration options should not be asserted during RESET#. Disabling of any of the cores within the Dual-Core Intel® Xeon® Processor 5200 Series must be handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the package.
Page 94: Normal State
RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either ® Normal Mode or the HALT state. See the Intel 64 and IA-32 Architecture Software Developer's Manual.
Page 95: Stop Clock State Machine
Table 7-2. Extended HALT Maximum Power (Sheet 2 of 2) Symbol Parameter Unit Notes 1 Extended HALT State EXTENDED_HALT Power Dual-Core Intel® Xeon® Processor E5240 Extended HALT State EXTENDED_HALT Power Dual-Core Intel® Xeon® Processor L5200 Series Extended HALT State EXTENDED_HALT Power Dual-Core Intel®...
Page 96: Stop-Grant State
Features 7.2.3 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no later than 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state.
Page 97: Enhanced Intel Speedstep® Technology
Not all Dual-Core Intel® Xeon® Processor 5200 Series are capable of supporting Enhanced Intel SpeedStep Technology. More details on which processor frequencies will support this feature will be provided in the Dual-Core Intel® Xeon® Processor 5200 Series Specification Update. Enhanced Intel SpeedStep Technology creates processor performance states (P-states)
Page 98 Features...
Page 99: Boxed Processor Specifications
The Dual-Core Intel® Xeon® Processor 5200 Series will be offered as an Intel boxed processor. Intel will offer the Dual-Core Intel® Xeon® Processor 5200 Series with two heat sink configurations available for each processor frequency: 1U passive/3U+ active combination solution and a 2U passive only solution.
Page 100: Boxed Dual-Core Intel® Xeon® Processor 5200 Series 1U Passive/3U+ Active Combination Heat Sink (With Removable Fan)
Boxed Processor Specifications Figure 8-1. Boxed Dual-Core Intel® Xeon® Processor 5200 Series 1U Passive/3U+ Active Combination Heat Sink (With Removable Fan) Figure 8-2. Boxed Dual-Core Intel® Xeon® Processor 5200 Series 2U Passive Heat Sink...
Page 101: Mechanical Specifications
Boxed Processor Specifications Figure 8-3. 2U Passive Dual-Core Intel® Xeon® Processor 5200 Series Thermal Solution (Exploded View) Notes: The heat sinks represented in these images are for reference only, and may not represent the final boxed processor heat sinks. The screws, springs, and standoffs will be captive to the heat sink. This image shows all of the components in an exploded view.
Page 102: Top Side Board Keepout Zones (Part 1)
Boxed Processor Specifications Figure 8-4. Top Side Board Keepout Zones (Part 1)
Page 103: Top Side Board Keepout Zones (Part 2)
Boxed Processor Specifications Figure 8-5. Top Side Board Keepout Zones (Part 2)
Page 104: Bottom Side Board Keepout Zones
Boxed Processor Specifications Figure 8-6. Bottom Side Board Keepout Zones...
Page 105: Board Mounting-Hole Keepout Zones
Boxed Processor Specifications Figure 8-7. Board Mounting-Hole Keepout Zones...
Page 106: Volumetric Height Keep-Ins
Boxed Processor Specifications Figure 8-8. Volumetric Height Keep-Ins...
Page 107: Pin Fan Cable Connector (For Active Cek Heat Sink)
Boxed Processor Specifications Figure 8-9. 4-Pin Fan Cable Connector (For Active CEK Heat Sink)
Page 108: Pin Base Board Fan Header (For Active Cek Heat Sink)
Boxed Processor Specifications Figure 8-10. 4-Pin Base Board Fan Header (For Active CEK Heat Sink)
Page 109: Boxed Processor Heat Sink Weight
Boxed Processor Specifications 8.2.2 Boxed Processor Heat Sink Weight 8.2.2.1 Thermal Solution Weight The 1U passive/3U+ active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams. Note that this is per processor, a dual processor system will have up to 2010 grams total mass in the heat sinks.
Page 110: Boxed Processor Cooling Requirements
Boxed Processor Specifications The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power header identification and location must be documented in the suppliers platform documentation, or on the baseboard itself. The baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket.
Page 111: Boxed Processor Contents
5°C with an external ambient temperature RISE of 35°C. These specifications apply to both copper and aluminum heatsink solutions. Following these guidelines allows the designer to meet Dual-Core Intel® Xeon® Processor 5200 Series Thermal Profile and conform to the thermal requirements of the processor.
Page 112 Boxed Processor Specifications §...
Page 113: Debug Tools Specifications
Debug Port System Requirements The Dual-Core Intel® Xeon® Processor 5200 Series debug port is the command and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the processors for system debug. The debug port, which is connected to the FSB, is a combination of the system, JTAG and execution signals.
Page 114: Mechanical Considerations
Debug Tools Specifications 9.3.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI plugs into the socket, while the processor plugs into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer.

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Intel E5205 - Cpu Xeon 1.86Ghz Fsb1066Mhz 6M Lga771 Dual Core Tray Datasheet

1 Introduction

2 Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications

3 Mechanical Specifications

4 Land Listing

5 Signal Definitions

6 Thermal Specifications

7 Features

8 Boxed Processor Specifications

9 Debug Tools Specifications

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