Requesting Low-Power Idle States; Idle Power Management Breakdown Of The Processor Cores; Thread And Core C-State Entry And Exit - Intel Xeon Processor E5-1600 Datasheet

Power Management
Figure 4-1.

Idle Power Management Breakdown of the Processor Cores

Figure 4-2.

Thread and Core C-State Entry and Exit

C1
While individual threads can request low power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
4.2.3

Requesting Low-Power Idle States

The core C-state will be C1E if all actives cores have also resolved a core C1 state
or higher.
The primary software interfaces for requesting low power idle states are through the
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).
However, software may make C-state requests using the legacy method of I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
method of requesting C-states provides legacy support for operating systems that
initiate C-state transitions via I/O reads.
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
T h r e a d 0 T h r e a d 1
C o r e 0 S ta te
P r o c e s s o r P a c k a g e S ta te
MWAIT(C1), HLT
MWAIT(C1), HLT
(C1E Enabled)
P_LVL2 I/O Read
C1E
T h r e a d 0
C o r e N S ta te
C0 C0
MWAIT(C6),
P_LVL3 I/O Read
MWAIT(C3),
C3 C6
T h r e a d 1
MWAIT(C7),
P_LVL4 I/O Read
C7
91