Voltage And Current Specifications; Voltage Specification - Intel Xeon Processor E5-1600 Datasheet

Electrical Specifications
7.8.1

Voltage and Current Specifications

Table 7-11. Voltage Specification
Symbol Parameter
V VID V VID Range
CC CC
V Core Voltage
CC
(Launch - FMB)
V VID step size during
VID_STEP
a transition
(Vcc, Vsa,
Vccd)
V PLL Voltage
CCPLL
V I/O Voltage for DDR3
CCD
(V (Standard Voltage)
CCD_01,
V
CCD_23)
V I/O Voltage for
CCD
(V DDR3L (Low Voltage)
CCD_01.
V
CCD_23)
V (V Uncore Voltage
TT TTA,
(Launch - FMB)
VTTD)
V Vsa VID Range
SA_VID
V System Agent
SA
Voltage
(Launch - FMB)
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on final silicon
characterization.
2. Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have
different settings.
3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is
required.
4. The V voltage specification requirements are measured across the remote sense pin pairs (VCC_SENSE and
CC
VSS_VCC_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth
oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1M
minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external
noise from the system is not coupled in the scope probe.
5. The V and V voltage specification requirements are measured across the remote sense pin pairs (VTTD_SENSE and
TTA, TTD
VSS_VTTD_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth
oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1M
minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external
noise from the system is not coupled in the scope probe.
6. The V voltage specification requirements are measured across the remote sense pin pairs (VSA_SENSE and
SA
VSS_VSA_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth
oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1M
minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external
noise from the system is not coupled in the scope probe.
7. For the 8/6-core processor refer to
and corresponding Figure
associated with any particular current. Failure to adhere to this specification can shorten processor lifetime.
8. Minimum V and maximum I
CC
"Thermal Management Specifications". I
capable of drawing I
CC_MAX
over various time durations.
9. The processor should not be subjected to any static V
current. Failure to adhere to this specification can shorten processor lifetime.
10. This specification represents the V
Identification (VID)".
11. Baseboard bandwidth is limited to 20 MHz.
12. FMB is the flexible motherboard guidelines. See
13. DC + AC + Ripple = Total Tolerance
14. For Power State Functions see
15. V does not have a loadline, the output voltage is expected to be the VID value.
SA_VID
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
Voltage
Min
Plane
0.6
V See Table 7-13,
CC
V 0.955*V
CCPLL CCPLL_TYP
V 0.95*V
CCD CCD_TYP
V 0.95*V
CCD CCD_TYP
V 0.957*V
TT TT_TYP
V 0.6
SA
V V - 0.064
SA SA_VID
Table 7-13 and corresponding
7-4.The processor should not be subjected to any static V
are specified at the maximum processor case temperature (T
CC
is specified at the relative V
CC_MAX
for up to 5 seconds. Refer to
TTA,
reduction or V increase due to each VID transition, see
CC CC
Section 7.6
Section 7.1.9.3.5.
Typ Max
1.35
Table 7-14 and Figure 7-3,
5.0
1.8 1.045*V
1.5 1.05*V
1.35 1.075*V
1.05 1.043*V
0.965 1.20
V V
SA_VID SA_VID
Figure 7-3. For the 4/2-core processor refer to
CC
point on the V
CC_MAX
Figure 7-5 for further details on the average processor current draw
V level that exceeds the V
TTD
for FMB details.
Unit Notes
V
Figure 7-4 V 3, 4, 7, 8,
12, 14, 18
mV
V 11, 12, 13,
CCPLL_TYP
V 11, 13, 14,
CCD_TYP
16, 17
V 11, 13, 14,
CCD_TYP
16, 17
V 3, 5, 9, 12,
TT_TYP
V 2, 3, 14, 15
+ 0.064 V 3, 6, 12, 14,
Table 7-14
level that exceeds the V
CC_MAX
) shown in Section 5,
CASE
load line. The processor is
CC
associated with any particular
TT_MAX
Section 7.1.9.3, "Voltage
1
2, 3
10
17
13
19
169