Peci Dc Specifications; System Reference Clock (Bclk{0/1}) Dc Specifications; Smbus Dc Specifications - Intel Xeon Processor E5-1600 Datasheet

13. DRAM_PWR_OK_C{01/23}: Data Scrambling must be enabled for production environments. Disabling Data scrambling may
be used for debug and testing purposes only. Operating systems with Data Scrambling off will make the configuration out of
specification.
Table 7-17. PECI DC Specifications
Symbol Definition and Conditions
V Input Voltage Range
In
V Hysteresis
Hysteresis
V Negative-edge threshold voltage
N
V Positive-edge threshold voltage
P
I High level output source
SOURCE
V = 0.75 * V
OH
I High impedance state leakage to V
Leak+
V )
OL
C Bus capacitance per node
Bus
V Signal noise immunity above 300 MHz
Noise
Notes:
1. V supplies the PECI interface. PECI behavior does not affect V
TTD
2. It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and consequently, be
able to drive its output within safe limits (-0.150 V to 0.275*V
high level).
3. The leakage specification applies to powered devices on the PECI bus.
4. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional
nodes.
5. Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently limit the maximum bit
rate at which the interface can operate.
Table 7-18. System Reference Clock (BCLK{0/1}) DC Specifications
Symbol Parameter
V Differential Input High Voltage
BCLK_diff_ih
V Differential Input Low Voltage
BCLK_diff_il
V (abs) Absolute Crossing Point
cross
V (rel) Relative Crossing Point
cross
V Range of Crossing Points
cross
V Threshold Voltage
TH
I Input Leakage Current
IL
C Pad Capacitance
pad
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. These specifications are specified at
the processor pad.
2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK{0/1}_DN is equal to the falling
edge of BCLK{0/1}_DP.
3. V is the statistical average of the VH measured by the oscilloscope.
Havg
4. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
5. V can be measured directly using "Vtop" on Agilent* and "High" on Tektronix oscilloscopes.
Havg
6. V is defined as the total variation of all crossing voltages as defined in Note 3.
CROSS
7. The rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP.
8. For Vin between 0 and Vih.
Table 7-19. SMBus DC Specifications (Sheet 1 of 2)
Symbol
V Input Low Voltage
IL
178
TT
(V
TTD leak
Signal
Differential
Differential
Single Ended
Single Ended
Single Ended
Single Ended
N/A
N/A
Parameter
Min
-0.150
0.100 * V
TT
0.275 * V 0.500 * V
TT
0.550 * V 0.725 * V
TT
-6.0
=
50
N/A
0.100 * V
TT
min/max specification
TTD
for the low level and 0.725*V
TTD
Min
0.150
0.250
0.250 +
0.5*(VH - 0.5*(VH
avg
0.700)
N/A
Vcross - 0.1 Vcross + 0.1
0.9
Min
0.3*V
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Max Units Figure
V V
TT
V
V 7-1
TT
V 7-1
TT
mA
200 µA
10 pF
N/A V
p-p
to V +0.150 V for the
TTD TTD
Max
Unit Figure
N/A V 7-8
-0.150 V 7-8
7-7
0.550 V
7-9
0.550 +
- V 7-7
avg
0.700)
0.140 V 7-10
V
1.50 A
1.1 pF
Max Units
V
TT
Datasheet Volume One
1
Notes
2
2
3
4,5
1
Notes
2, 4, 7
3, 4, 5
6
8
Notes