Intel Xeon Processor E5-1600 Datasheet page 22

LLC
LRDIMM
NCTF
NEBS
PCH
PCU
PCI Express* 3.0
PCI Express* 3
PCI Express* 2
PCI Express*
PECI
Phit
Processor
Processor Core
RDIMM
Rank
Scalable-2S
SCI
SSE
SKU
SMBus
Storage Conditions
TAC
22
Term
Last Level Cache
Load Reduced Dual In-line Memory Module
Non-Critical to Function: NCTF locations are typically redundant ground or non-
critical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
Network Equipment Building System. NEBS is the most common set of
environmental design guidelines applied to telecommunications equipment in the
United States.
Platform Controller Hub (Intel® C600 Chipset). The next generation chipset with
centralized platform capabilities including the main I/O interfaces along with
display connectivity, audio features, power management, manageability, security
and storage features.
Power Control Unit
The third generation PCI Express* specification that operates at twice the speed
of PCI Express* 2.0 (8 Gb/s); however, PCI Express* 3.0 is completely backward
compatible with PCI Express* 1.0 and 2.0.
PCI Express* Generation 3.0
PCI Express* Generation 2.0
PCI Express* Generation 2.0/3.0
Platform Environment Control Interface
Physical Unit. An Intel® QPI terminology defining units of transfer at the physical
layer. 1 Phit is equal to 20 bits in 'full width mode' and 10 bits in 'half width
mode'
The 64-bit, single-core or multi-core component (package)
The term "processor core" refers to silicon die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache. All DC and signal
integrity specifications are measured at the processor die (pads), unless
otherwise noted.
Registered Dual In-line Memory Module
A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a DDR3
DIMM.
Intel® Xeon® processor E5 product family-based platform targeted for scalable
designs using third party Node Controller chip. In these designs, Node Controller
is used to scale the design beyond one/two/four sockets.
System Control Interrupt. Used in ACPI protocol.
Intel® Streaming SIMD Extensions (Intel® SSE)
A processor Stock Keeping Unit (SKU) to be installed in either server or
workstation platforms. Electrical, power and thermal specifications for these
SKU's are based on specific use condition assumptions. Server processors may
be further categorized as Efficient Performance server, workstation and HPC
SKUs. For further details on use condition assumptions, please refer to the latest
Product Release Qualification (PRQ) Report available via your Customer Quality
Engineer (CQE) contact.
System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the
system. It is based on the principals of the operation of the I2C* two-wire serial
bus from Philips Semiconductor.
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to "free air"
(i.e., unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
Thermal Averaging Constant
Description
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Overview
Datasheet Volume One