ADTRAN ATLAS 800 SERIES System Manual page 129

ATLAS 800 Series System Manual
PLL/FIFO
Read security: 5
Displays the Phase Lock Loop (PLL) and FIFO status.
Port
PLL/FIFO
State
Lock
RXE
RXF
TXE
TXF
Configuration
Write security: 3; Read security: 5
All of the following configurable parameters apply to the individual USSI ports.
Prt
Name
Clk +/-
Data
CTS
DCD
61200780L1-1C
Indicates the operating port.
Displays the state of the PLL and FIFO systems:
Description
PLL is locked (This is required to transfer data.)
Receive data FIFO empty.
Receive data FIFO full.
Transmit data FIFO empty.
Transmit data FIFO full.
Read security: 5
Displays the port number.
Accepts any alpha-numeric name up to 15 characters long, to uniquely identify
each port on the Quad USSI Option Module.
Controls the clock used by the ATLAS 800 Series to accept the transmit (TX)
data from the DTE. This is usually set to
causing a phase shift in the data, the clock can be set to
the phase of the clock, which compensates for a long cable.
Controls the inverting of the DTE data. This inversion can be useful when
operating with a high-level data link control (HDLC) protocol (often used as a
means to ensure 1s density). Select either
configuration must match at both ends of the circuit.
Determines the behavior of the Clear To Send (
will follow the value of Request To Send (
CTS
will always be asserted.
Write security: 3; Read security: 5
Determines the behavior of the Data Carrier Detect (DCD) signal, also called
RLSD on some interfaces. If set to
when the interface is capable of passing data (consult the ATLAS 800 Series
© 2004 ADTRAN, Inc.
. If the interface cable is long,
N
ORMAL
I
NVERTED
N or I
ORMAL NVERTED
) signal. If set to
CTS
). If set to
RTS
N , DCD will generally be asserted
ORMAL
USSI Option Module
PLL/FIFO
. This switches
. Data inversion
N ,
ORMAL
F O , CTS
ORCED N
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