Signal Groups - Intel PENTIUM P6000 - DATASHEET 2010 Datasheet

7.6

Signal Groups

Signals are grouped by buffer type and similar characteristics as listed in
The buffer type indicates which signaling technology and specifications apply to the
signals. All the differential signals, and selected DDR3 and Control Sideband signals
have On-Die Termination (ODT) resistors. There are some signals that do not have ODT
and need to be terminated on the board.
Table 7-38.Signal Groups
Signal Group
System Reference Clock
Differential
Differential
DDR3 Reference Clocks
Differential
DDR3 Command Signals
Single Ended
2
DDR3 Data Signals
Single ended
Differential
TAP (ITP/XDP)
Single Ended
Single Ended
Single Ended
Single Ended
90
1
(Sheet 1 of 3)
Alpha
Type
Group
(a) CMOS Input
(b) CMOS Output
2
(c) DDR3 Output
2
(d) DDR3 Output
(e) DDR3 Bi-directional
(f) DDR3 Bi-directional
(g) CMOS Input
(ga) CMOS Input
(h) CMOS Open-Drain
Output
(i) Asynchronous
CMOS Output
Electrical Specifications
Signals
BCLK, BCLK#
PEG_CLK, PEG_CLK#
DPLL_REF_SSCLK, DPLL_REF_SSCLK#
BCLK_ITP, BCLK_ITP#
SA_CK[1:0], SA_CK#[1:0]
SB_CK[1:0], SB_CK#[1:0]
SA_RAS#, SB_RAS#, SA_CAS#, SB_CAS#
SA_WE#, SB_WE#
SA_MA[15:0], SB_MA[15:0]
SA_BS[2:0], SB_BS[2:0]
SA_DM[7:0], SB_DM[7:0]
SM_DRAMRST#
SA_CS#[1:0], SB_CS#[1:0]
SA_ODT[1:0], SB_ODT[1:0]
SA_CKE[1:0], SB_CKE[1:0]
SA_DQ[63:0], SB_DQ[63:0]
SA_DQS[7:0], SA_DQS#[7:0]
SB_DQS[7:0], SB_DQS#[7:0]
TCK, TMS, TRST#
TDI,TDI_M
TDO, TDO_M
TAPPWRGOOD
Table 7-38.
Datasheet