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Table 7-43.Processor Graphics VID based (V
Specifications
Symbol
GFX_VID
VID Range for V
SV
ULV
V
Graphics core voltage
AXG
TOL
V
Tolerance
AXG
AXG
Non-VR LL
Non-VR Load Line Contribution for
contribution
V
AXG
rPGA
BGA
LL
V
Loadline
AXG
AXG
I
Max Current for Integrated
CCMAX_VAXG
Graphics Rail
SV
ULV
I
Thermal Design Current
CCTDC_VAXG
(TDC) for Integrated Graphics Rail
SV
ULV
NOTES:
1.
These are pre-silicon estimates and are subject to change.
2.
Minimum values assume Graphics Render C-state (RC6) is enabled.
3.
V
is a VID-Based rail driven by an Intel MVP6.5 compliant voltage regulator.
AXG
4.
This specification assumes Intel Turbo Boost Technology with Intelligent Power Sharing is enabled.
Figure 7-15.V
/I
AXG
98
Parameter
AXG
Static and Ripple Voltage Regulation
AXG
Slope = LL
Differential Remote Sense required.
V
=
AXG_MAX
V
+2.2%*GFX_VID
AXG_NOM
V
= GFX_VID
AXG_NOM
V
=
AXG_MIN
V
-LL
*I
AXG_NOM
AXG
CCMAX_VAXG
-2.2%*GFX_VID
0
) Supply DC Voltage and Current
AXG
Min
Typ
0
0
See
Figure 7-15
See
Figure 7-15
4
4.25
-7
-
-
V
[V]
AXG
at package VAXG_SENSE, and VSSAXG_SENSE pins
AXG
+ / - V I D * 2 . 2 %
V
Total tolerance window (GFX_DPRSLPVR de-asserted)
AXG
DC (set point +LL tolerance)+ AC (ripple)
for Standard and Enhanced Performance Frequency Modes
Electrical Specifications
Max
Unit
Note
1.4
V
2,3,4
1.35
mΩ
mΩ
A
4
22
12
A
4
12
6
I
[A]
AXG
I
CCMAX_VAXG
Datasheet
1
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