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Table 4-13.Coordination of Thread Power States at the Core Level
Processor Core
C-State
NOTE:If enabled, the core C-state will be C1E if all actives cores have also resolved a
core C1 state or higher
4.2.3
Requesting Low-Power Idle States
The primary software interfaces for requesting low power idle states are through the
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).
However, software may make C-state requests using the legacy method of I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
method of requesting C-states provides legacy support for operating systems that
initiate C-state transitions via I/O reads.
For legacy operating systems, P_LVLx I/O reads are converted within the processor to
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in
I/O reads to the system. The feature, known as I/O MWAIT redirection, must be
enabled in the BIOS.
Note:
The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read
interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as follows.
Table 4-14.P_LVLx to MWAIT Conversion
P_LVLx
P_LVL2
P_LVL3
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any
P_LVLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx) like
request. They fall through like a normal I/O instruction.
Note:
When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The
MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O
redirections enable the MWAIT 'break on EFLAGS.IF' feature which triggers a wakeup
on an interrupt even if interrupts are masked by EFLAGS.IF.
42
C0
C0
C0
C0
C1
C0
C3
C0
C6
MWAIT(Cx)
MWAIT(C3)
The P_LVL2 base address is defined in the PMG_IO_CAPTURE
MSR, described in the RS - Nehalem Processor Family BWG.
MWAIT(C6)
C6. No sub-states allowed.
Thread 1
C1
C3
C0
C0
1
1
C1
C1
1
C1
C3
1
C1
C3
Notes
Power Management
C6
C0
1
C1
C3
C6
Datasheet
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