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Electrical Specifications
Table 7-48.PECI DC Electrical Limits
Symbol
Definition and Conditions
V
Input Voltage Range
in
V
Hysteresis
hysteresis
V
Negative-edge Threshold Voltage
n
V
Positive-edge Threshold Voltage
p
I
High-Level Output Source
source
(V
= 0.75 * V
OH
I
Low-Level Output Sink
sink
(V
= 0.25 * V
OL
I
High-Impedance State Leakage to V
leak+
(V
= V
leak
OL
I
High-Impedance Leakage to GND
leak-
(V
= V
leak
OH
C
Bus Capacitance Per Node
bus
V
Signal Noise Immunity above 300 MHz
noise
NOTES:
1.
V
supplies the PECI interface. PECI behavior does not affect V
TT
2.
The leakage specification applies to powered devices on the PECI bus.
7.11.2
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use
Figure 7-16.Input Device Hysteresis
V
Maximum V
Minimum V
Maximum V
Minimum V
PECI Ground
Datasheet
)
TT
)
TT
TT
)
)
TTD
PECI High Range
P
P
N
PECI Low Range
N
Min
Max
-0.150
V
TT
0.1 * V
N/A
TT
0.275 * V
0.500 * V
TT
0.550 * V
0.725 * V
TT
-6.0
N/A
0.5
1.0
N/A
100
N/A
100
N/A
10
0.1 * V
N/A
TT
min/max specifications.
TT
Figure 7-16
as a guide for input buffer design.
Minimum
Hysteresis
1
Units
Notes
V
V
V
TT
V
TT
mA
mA
µA
2
µA
2
pF
V
p-p
Valid Input
Signal Range
103
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