Figure 4-9 Idle Power Management Breakdown Of The Processor Cores; Figure 4-10 Thread And Core C-State Entry And Exit - Intel PENTIUM P6000 - DATASHEET 2010 Datasheet

Power Management
Figure 4-9. Idle Power Management Breakdown of the Processor Cores
Entry and exit of the C-States at the thread and core level are shown in below figure.
Figure 4-10.Thread and Core C-State Entry and Exit
C1
While individual threads can request low power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
Datasheet
Thread 0
Core 0 State
Processor Package State
MWAIT(C1), HLT
MWAIT(C1), HLT
(C1E Enabled)
C1E
Thread 0
Core 1 State
C0 C0
MWAIT(C3),
P_LV2 I/O Read
C3
MWAIT(C6),
P_LVL3 I/O Read
C6
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