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Features Summary
1.7
Terminology
BLT
CRT
DDR3
DP
DMA
DMI
DTS
ECC
eDP*
Intel® DPST
Enhanced Intel
SpeedStep®
Technology
Execute Disable Bit
(G)MCH
GPU
ICH
IMC
Intel® 64 Technology
ITPM
IOV
LCD
LVDS
MCP
NCTF
Nehalem
Datasheet
Term
Block Level Transfer
Cathode Ray Tube
Third-generation Double Data Rate SDRAM memory technology
DisplayPort*
Direct Memory Access
Direct Media Interface
Digital Thermal Sensor
Error Correction Code
Embedded DisplayPort*
®
Intel
Display Power Saving Technology
Technology that provides power management capabilities to laptops.
The Execute Disable bit allows memory to be marked as executable or
non-executable, when combined with a supporting operating system.
If code attempts to run in non-executable memory the processor
raises an error to the operating system. This feature can prevent some
classes of viruses or worms that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. See the
Intel® 64 and IA-32 Architectures Software Developer's Manuals for
more detailed information.
Legacy component - Graphics Memory Controller Hub
Graphics Processing Unit
The legacy I/O Controller Hub component that contains the main PCI
interface, LPC interface, USB2, Serial ATA, and other I/O functions. It
communicates with the legacy (G)MCH over a proprietary interconnect
called DMI.
Integrated Memory Controller
64-bit memory extensions to the IA-32 architecture
Integrated Trusted Platform Module
I/O Virtualization
Liquid Crystal Display
Low Voltage Differential Signaling. A high speed, low power data
transmission standard used for display connections to LCD panels.
Multi-Chip Package.
Non-Critical to Function. NCTF locations are typically redundant
ground or non-critical reserved, so the loss of the solder joint
continuity at end of life conditions will not affect the overall product
functionality.
Intel's 45-nm processor design, follow-on to the 45-nm Penryn design.
Description
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