Intel PENTIUM P6000 - DATASHEET 2010 Datasheet page 18

PCH
PECI
PEG
Processor
Processor Core
Rank
SCI
Storage Conditions
TAC
TDP
V
CC
V
SS
V
AXG
V
TT
V
DDQ
VLD
x1
x4
x8
x16
18
Term
Platform Controller Hub. The new, 2009 chipset with centralized
platform capabilities including the main I/O interfaces along with
display connectivity, audio features, power management,
manageability, security and storage features. The PCH may also be
referred to using the name (Mobile) Intel® 5 Series Chipset
Platform Environment Control Interface.
PCI Express* Graphics. External Graphics using PCI Express
Architecture. A high-speed serial interface whose configuration is
software compatible with the existing PCI specifications.
The 64-bit, single-core or multi-core component (package).
The term "processor core" refers to Si die itself which can contain
multiple execution cores. Each execution core has an instruction
cache, data cache, and 256-KB L2 cache. All execution cores share the
L3 cache.
A unit of DRAM corresponding four to eight devices in parallel, ignoring
ECC. These devices are usually, but not always, mounted on a single
side of a SO-DIMM.
System Control Interrupt. Used in ACPI protocol.
A non-operational state. The processor may be installed in a platform,
in a tray, or loose. Processors may be sealed in packaging or exposed
to free air. Under these conditions, processor landings should not be
connected to any supply voltages, have any I/Os biased or receive any
clocks. Upon exposure to "free air" (i.e., unsealed packaging or a
device removed from packaging material) the processor must be
handled in accordance with moisture sensitivity labeling (MSL) as
indicated on the packaging material.
Thermal Averaging Constant.
Thermal Design Power.
Processor core power supply.
Processor ground.
Graphics core power supply.
L3 shared cache, memory controller, and processor I/O power rail.
DDR3 power rail.
Variable Length Decoding.
Refers to a Link or Port with one Physical Lane.
Refers to a Link or Port with four Physical Lanes.
Refers to a Link or Port with eight Physical Lanes.
Refers to a Link or Port with sixteen Physical Lanes.
Features Summary
Description
Datasheet