Voltage Regulator (Mvr) To Processor Package Interface; Processor To Mvr Interface Loads; Processor Package Load Limits At Power Tab - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

Mechanical Specifications
4.1.1

Voltage Regulator (MVR) to Processor Package Interface

Critical package mechanical requirements at its interface with the MVR are identified in
Figure 4-6
must comply during and after installation are outlined in
are intended to minimize potential damage to the processor that may result from
installation of the MVR.
Figure 4-6.

Processor to MVR Interface Loads

X
X
Table 4-3. Processor Package Load Limits at Power Tab (Sheet 1 of 2)
Parameter
A
P
d
Tz
® ®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
and Table 4-3. The processor interface boundary conditions with which MVR
Y
90
T
Z
Z
P
T
y 90
A
P
Description
Final position of the package at the
power tab (unloaded) with respect to
system board
Allowable load on the package in +z
and -z direction
Allowable displacement at the
processor power tab in z direction
under load P
Allowable torque on the package tip in
z axis
Table
P ro ce s so r H e ats in k
-z
P ro ce s so r H e ats in k
IH S
S o c ke t
+z
1
Value
3.8+/- Position of the processor power tab is
0.1mm based on the height of the mPGA700
ZIF socket height from the mother
post SMT
22.25N max
+/- 0.3 mm
max
0 Package loading in Y direction is not
allowed. Hence, zero torque in Z-axis
4-3. These requirements
S u b stra te
M oth er B oa rd
Comments
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