Itanium ® Processor System Bus Signal Groups - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

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Table 2-1. Itanium
Group Name
AGTL+ Input Signals
AGTL+ I/O Signals
AGTL+ Output Signals
Special AGTL+ Asynchronous
Interrupt Input Signals
Power Good Signal
HSTL Clock Signals
TAP Input Signals
TAP Output Signals
System Management Signals
Power Signals
LVTTL Power Pod Signals
Other
Notes:
1. Signals will not be terminated on-die even when on-die termination (ODT) is enabled. See the Intel
2 Processor Hardware Developer's Manual for further details.
All system bus outputs should be treated as open drain signals and require a high-level
source provided by the V
AGTL+ inputs have differential input buffers which use V
output signals require termination to V
refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving.
Similarly, "AGTL+ Output Signals" refers to the AGTL+ output group as well as the
AGTL+ I/O group when driving.
The Test Access Port (TAP) connection input signals use a non-differential receiver with
levels that are similar to AGTL+. No reference voltage is required for these signals. The
TAP Connection Output signals are AGTL+ output signals.
The processor system bus requires termination on both ends of the bus. The processor
system bus supports both on-die and off-die termination controlled by two pins, TERMA
and TERMB. Please see the TERMA and TERMB pin description in
The HSTL clock signals are the differential clock inputs for the processor. The SMBus
signals and LVTTL power pod signals are driven using the 3.3 V CMOS logic levels listed
in Table 2-8
16
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Processor System Bus Signal Groups
BPRI#, BR[3:1]#, DEFER#, GSEQ#, ID[9:0]#, IDS#, RESET#
RSP#, TRDY#
A[49:3]#, ADS#, AP[1:0]#, BERR#, BINIT#, BNR#, BPM[5:0]#
D[127:0]#, DBSY#, DEP[15:0]#, DRDY#, HIT#, HITM#, LOCK#,
REQ[5:0]#, RP#, SBSY#, STBN[7:0]#, STBP[7:0]#, TND#
FERR#, THRMTRIP#, DBSY[1:0]#, DRDY[1:0]#, SBSY[1:0]#
A20M#, IGNNE#, INIT#, LINT[1,0], PMI#
1
PWRGOOD
BCLKn, BCLKp
1
TCK, TDI, TMS, TRST#
1
TDO
1
3.3 V, SMA[2:0], SMSC, SMSD, SMWP, THRMALERT#
GND, VCTERM
1
CPUPRES#, OUTEN, PPODGD#
TERMA, TERMB, TUNER1, TUNER2, TUNER3, VCCMON, VSSMON
supply.
CTERM
and Table 2-9, respectively.
Signals
. In this document, "AGTL+ Input Signals"
CTERM
® ®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
1
, RS[2:0]#,
1
, BR0#,
®
as a reference level. AGTL+
REF
Section 2.2.2.
®
Itanium