Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual page 5

A.1.45 LOCK# (I/O)........................................................................................ 100
A.1.46 NMI (I) ............................................................................................... 101
A.1.47 OWN# (I/O) ........................................................................................ 101
A.1.48 PMI# (I) ............................................................................................. 101
A.1.49 PWRGOOD (I) ...................................................................................... 101
A.1.50 REQ[5:0]# (I/O) .................................................................................. 101
A.1.51 RESET# (I) ......................................................................................... 102
A.1.52 RP# (I/O) ........................................................................................... 102
A.1.53 RS[2:0]# (I) ....................................................................................... 103
A.1.54 RSP# (I) ............................................................................................. 103
A.1.55 SBSY# (I/O)........................................................................................ 103
A.1.56 SBSY_C1# (O)..................................................................................... 103
A.1.57 SBSY_C2# (O)..................................................................................... 103
A.1.58 SPLCK# (I/O) ...................................................................................... 103
A.1.59 STBn[7:0]# and STBp[7:0]# (I/O) ......................................................... 103
A.1.60 TCK (I) ............................................................................................... 104
A.1.61 TDI (I)................................................................................................ 104
A.1.62 TDO (O).............................................................................................. 104
A.1.63 THRMTRIP# (O) ................................................................................... 104
A.1.64 THRMALERT# (O)................................................................................. 104
A.1.65 TMS (I) ............................................................................................... 104
A.1.66 TND# (I/O) ......................................................................................... 104
A.1.67 TRDY# (I) ........................................................................................... 105
A.1.68 TRST# (I) ........................................................................................... 105
A.1.69 WSNP# (I/O)....................................................................................... 105
A.2 Signal Summaries ........................................................................................... 105
Figures
2-1 Generic Clock Waveform .................................................................................... 21
2-2 SMSC Clock Waveform ....................................................................................... 22
2-3 System Bus Signal Waveform Exhibiting Overshoot/Undershoot............................... 23
2-4 Processors Power Tab Physical Layout .................................................................. 28
2-5 System Bus Reset and Configuration Timings for Cold Reset.................................... 31
2-6 System Bus Reset and Configuration Timings for Warm Reset ................................. 32
3-1 Dual-Core Intel
4-1 Processor Package............................................................................................. 66
4-2 Package Height and Pin Dimensions ..................................................................... 67
4-3 Processor Package Mechanical Interface Dimensions .............................................. 69
4-4 Processor Package Top-Side Components Height Dimensions .................................. 70
4-5 Processor Package Bottom-Side Components Height Dimensions ............................. 70
4-6 Processor to MVR Interface Loads ........................................................................ 71
4-7 Processor Top-Side Marking on IHS ..................................................................... 73
4-8 Processor Bottom-Side Marking Placement on Interposer ........................................ 74
5-1 Dual-Core Intel
Features .......................................................................................................... 75
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5-2 Itanium Processor Package Thermocouple Location .............................................. 77
6-1 Logical Schematic of SMBus Circuitry ................................................................... 80
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Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
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Itanium Processor 9000 and 9100 Series Pinout.......................... 35
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Itanium Processor 9000 and 9100 Series Thermal
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