Agtl+ Signals Dc Specifications; Power Good Signal Dc Specifications; System Bus Clock Differential Hstl Dc Specifications; Tap Connection Dc Specifications - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

Dual-core intel itanium processor 9000 and 9100 series
Hide thumbs Also See for P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor:
Table of Contents

Advertisement

Electrical Specifications
Table 2-4.

AGTL+ Signals DC Specifications

Symbol
V
IL
V
IH
V
OL
V
OH
I
OL
I
OL
I
L
C
AGTL+
Notes:
1. The typical transition point between V
V
REF_low
and V
REF_low
2. Parameter measured into a 22.5 ohm resistor to 1.2 V. Minimum V
characterization.
3. Calculated using off-die termination through two 45 ohm ±1% resistors in parallel.
4. Calculated using on-die termination to a 45 ±15% resistor measured at V
5. At 1.2 V ±1.5%. V
6. Total of I/O buffer with ESD structure and processor parasitics if applicable. Capacitance values guaranteed
by design for all AGTL+ buffers.
Table 2-5.

Power Good Signal DC Specifications

Symbol
V
IL
V
IH
Table 2-6.

System Bus Clock Differential HSTL DC Specifications

Symbol
V
IH
V
IL
V
X
C
CLK
Table 2-7.

TAP Connection DC Specifications

Symbol
V
IL
V
IH
V
OL
V
OH
I
OL
I
IC
Notes:
1. There is a 100 mV hysteresis on TCK.
2. V
IH, MAX
3. There is no internal pull-up. An external pull-up is always assumed. Max voltage tolerated at TDO is 1.5 V.
4. Per input pin.
®
®
Dual-Core Intel
Itanium
Processor 9000 and 9100 Series Datasheet
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current @ 0.3 V
Output Low Current @ 0.3 V
Leakage Current
AGTL+ Pad Capacitance
levels are V
±100 mV, respectively, for a system bus agent using on-board termination. V
REF
levels are V
±125 mV, respectively, for a system bus agent using on-die termination.
REF
, minimum Vpin V
CTERM
Parameter
Input Low Voltage
Input High Voltage
Parameter
Input High Voltage
Input Low Voltage
Input Crossover Voltage
Input (Pad) Capacitance
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Input Current
= 1.5 V + 5%, V
= 1.2 V +5%.
OH, MAX
Core
Minimum
Frequency
All
All
0.875
All
All
V
,
CTERM
minimum
All
34
All
17
All
All
and V
assuming 125 mV V
IL
IH
OL
, maximum.
CTERM
Minimum
0.875
Minimum
0.78
–0.3
0.55
Minimum
–0.3
1.1
1.2
20
Typ
Maximum
Unit
0.625
V
V
0.3
0.4
V
V
V
,
V
CTERM
CTERM
maximum
mA
mA
±100
µA
2
pF
uncertainty for ODT. V
REF
REF_high
and I
are guaranteed by design/
OL
.
OL
Maximum
Unit
Notes
0.440
V
V
Maximum
Unit
Notes
1.3
V
0.5
V
0.85
V
1.75
pF
Maximum
Unit
Notes
0.5
V
1.57
V
0.3
V
V
mA
690
uA
Notes
1
1
2
3
4
5
6
and
REF_high
1
1, 2
2, 3
4
19

Advertisement

Table of Contents
loading

Table of Contents