Trdy# (I); Trst# (I); Wsnp# (I/O); Signal Summaries - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

Signals Reference
A.1.67

TRDY# (I)

The Target Ready (TRDY#) signal is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer.
A.1.68

TRST# (I)

The TAP Reset (TRST#) signal is an IEEE 1149.1 compliant TAP support signal used by
debug tools.
A.1.69

WSNP# (I/O)

The Write Snoop (WSNP#) signal indicates that snooping agents will snoop the memory
write transaction
A.2

Signal Summaries

Table A-12
signals.
Table A-12. Output Signals
Name
CPUPRES#
DBSY_C1#
DBSY_C2#
DRDY_C1#
DRDY_C2#
FERR#
SBSY_C1#
SBSY_C2#
TDO
THRMTRIP#
THRMALERT#
Table A-13. Input Signals (Sheet 1 of 2)
Name
BPRI#
BR1#
BR2#
BR3#
BCLKp
BCLKn
D/C#
DEFER#
DHIT#
GSEQ#
® ®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
through Table A-15 list attributes of the processor output, input, and I/O
Active Level
Low
Low
Low
Low
Low
Low Asynchronous
Low
Low
High
Low Asynchronous
Low Asynchronous
Active Level
Low
Low
Low
Low
High
High
Low
Low
Low
Low
Clock Signal Group
— Platform
BCLKp Data
BCLKp Data
BCLKp Data
BCLKp Data
PC Compatibility,
IERR Mode
BCLKp Data
BCLKp Data
TCK TAP
Error
Error
Clock Signal Group
BCLKp Arbitration
BCLKp Arbitration
BCLKp Arbitration
BCLKp Arbitration
— Control
— Control
BCLKp System Bus
BCLKp Snoop
BCLKp System Bus
BCLKp Snoop
Qualified
Always
Always
Always
Always
Always
Always
Request Phase (Mem Rd)
Snoop Phase
IDS#+1
Snoop Phase
105